1. Analog front-end for vertically integrated hybrid and monolithic pixels L. Ratti Università degli Studi di Pavia and INFN Pavia XV SuperB General Meeting December 14-17 2010 CalTech - Pasadena, USA OUTLINE Vertical integration CMOS technology Analog front-end for 3D MAPS general features compensation for voltage drop on supply/ground 3D analog front-end for hybrid pixels general features threshold correction University of Bergamo and INFN Pavia Luigi Gaioni, Massimo Manghisoni, Valerio Re, Gianluca Traversi University of Pavia and INFN Pavia Alessia Manazza, Lodovico Ratti, Stefano Zucca

2. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting 3D technology options for the SuperB SVT Hybrid pixel detectors Design of the SVT layer0 at SuperB has to comply with severe requirements large background, >5 MHz/cm 2, small thickness, <1% X 0 vertically integrated, mixed-signal circuit to read out a standard pixel detector in high resistivity silicon (a 128x32 channel chip to be submitted in the next run) fine pitch (50 μm) bump bonding (IZM, Munich), other technologies (direct bonding by Ziptronix or T-Micro) might be investigated in the future Deep N-well CMOS monolithic sensors (DNW-MAPS) innovative approach (deep N-well sensor) proposed to enable fast readout through pixel-level sparsification and time stamping (a 128x100 pixel chip is being designed for the next run) Two options made available by vertical integration technologies (3D) are being pursued based on extensive R&D in planar 130 nm CMOS technology DNW sensor in an undepleted substrate, analog front-end for capacitive detectors, analog and digital blocks integrated in separate layers

3. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Vertical integration (3D) technologies In wafer-level, three-dimensional processes, multiple strata of planar devices are stacked and interconnected using through silicon vias (TSV) Fabrication of electrically isolated connections through the silicon substrate (TSV formation) Substrate thinning (below 50 μm) 3D processes rely upon the following enabling technologies Inter-layer alignment and mechanical/electrical bonding Tezzaron Semiconductor technology (via first approach) can be used to vertically integrate two 130 nm CMOS layers specifically processed by Chartered Semiconductor 1 st wafer 2 nd wafer WB/BB pad TSV Inter-tier bond pads

4. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting From 2D to 3D MAPS Analog section Digital section DNW sensor P-well N-well NMOS PMOS Digital section DNW sensor Analog section Analog and digital blocks integrated in separate layers to minimize cross-talk between digital blocks and sensor/analog circuits Tier 1: collecting electrode and mainly NMOS parts from the analog front-end Tier 2: PMOS parts from the analog front-end, digital front-end and peripheral digital readout electronics less PMOS in the sensor layer  improved collection efficiency more room for both analog and digital power and signal routing (in planar CMOS MAPS scaling to suitably large matrices is forbidden by the need for point-to-point lines from macropixels to periphery)

5. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Analog front-end for the ApselVI 3D MAPS chip CFCF C1C1 C2C2 V THR V REF A(s) Total power dissipation=37 μ W C D =300 fF Charge sensitivity: 730 mV/fC ENC: 33 electrons 375 ns peaking time W/L=32/0.25, I D,PA =15  A Threshold dispersion: 60 electrons INL: ~1% (@ 4000 e - ) Design features and simulation results

6. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Voltage drop on analog power/ground lines 256x50 μm 192x50 μm May be an issue with large matrices of relatively current-hungry detectors (e.g. DNW MAPS) Power distribution with a single thick metal layer (M5 in Chartered CMOS tech) AVDD width=AGND width=24 μ m Max density=80%  eq. width≈19 μm I cell =25  A M5 sheet resistance=25/35 m  / □ (typ/max)  R cell ≈65/90 m  (typ/max)  V d =15/20 mV (typ/max) Total current ~1.3 A  at least 40 AVDD PADS and 40 AGND PADS required to have ~30 mA/pad or less 1.5 W/cm 2 @ AVDD=1.5 V Front-end features can degrade due to voltage drop on the power and ground lines causing changes in some pixel current sources – shaper input branch and transconductor

7. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Voltage drop compensation: shaper input branch R. Szczygiel et al., “A Prototype Pixel Readout IC for High Count Rate X- Ray Imaging Systems in 90 nm CMOS Technology”, IEEE TNS, vol. 57, no. 3 June 2009, pp. 1664-1674 current source of the shaper input device V peri V pixel GND peri GND pixel To avoid the effect of voltage drop on the current source in the shaper input branch, two reference voltages, V g and V s are distributed to the pixels IbIb IbIb IrIr I rs VgVg VsVs M1M1 MsMs I rs ≈I r, provided that M 1 and M s have the same gate dimensions and I b >>I rs May determine a non negligible increase in power dissipation, requires running two more bias lines across each matrix row

8. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting M. Manghisoni et al., “High Accuracy Injection Circuit for Pixel-Level Calibration of Readout Electronics”, 2010 IEEE NSS Conference Record Voltage drop compensation: transconductor from shaper output to shaper input V peri V pixel GND peri GND pixel RR The current mirror accuracy is improved by means of a feedback loop in the pixel Provided that the amplifier gain is large enough, current I t is adjusted in such a way that V SG in transistor M t equals V s -V g in the diode connected transistor M 1 Some PMOS transistors are added (should actually be avoided in MAPS design) – amplifier, current source and transconductor PMOS might be moved to the second layer M1M1 VgVg VsVs MtMt ItIt IbIb

9. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Effects on output waveform w/o voltage drop compensationwith voltage drop compensation AVDD=1.2 V- ΔV d, AGND=ΔV d Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines

10. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Effects on charge sensitivity and peaking time AVDD=1.2 V- ΔV d, AGND=ΔV d Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines, namely

11. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting 3D hybrid pixels Analog section Digital section detector layer Bump bonding (e.g. IZM) Direct bonding (e.g. Ziptronix) 1 st layer 2nd layer detector layer Development of a 3D front-end chip to be vertically integrated with fully depleted detectors through some more (bump bonding) or less (direct bonding) standard technique Larger signal available from the detector (≥ 4000 e - for 200 μm thickness ) More advantageous trade-off between S/N and dissipated power

12. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Analog FE for the SuperPix1 hybrid pixel readout chip CFCF C1C1 C2C2 V GTHR THR DAC shift-in shift-out Total power dissipation=7 μ W C D =150 fF Charge sensitivity (G Q ): 45 mV/fC ENC: 130 electrons 300 ns peaking time Design features and simulation results W/L=18/0.25, I D,PA =2.5  A Threshold dispersion: 380 electrons INL: ~3% (@ 64000 e - )

13. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Threshold dispersion correction If the threshold voltages in a multichannel chip follow a Gaussian distribution, a minimum of the correction factor (  th,c /  th ) with respect to the DAC range can be found For DAC range values ≥ optimum value, the correction factor gets closer to the theoretical value obtained in the case of uniform distribution of the threshold voltages across the DAC range threshold voltage counts

14. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting 4-bit current steering DAC V GTHR shift-in shift-out shift-in shift-out CLK I+I+ I-I- I+I+ I-I- C2C2 CSEL I LSB I + LSB I - LSB Thermometric decoder Thermometric, sequential selection by lines and columns starting from one corner of the array Increase in overall power dissipation, slight complication for the slow control section reg

15. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Conclusion and future plans Both MAPS and hybrid pixels can gain significant benefits from going 3D The design of the analog front-end for monolithic and hybrid pixels in a 130 nm vertically integrated CMOS technology is almost completed (some work still to be done on DACs for threshold correction) increase in charge collection efficiency immunity from (or reduction of) cross-talk phenomena between digital blocks and sensor/analog circuits Measures have been adopted to compensate for the voltage drop on the power/ground lines in MAPS and to reduce threshold dispersion effects in hybrid pixels better trade-off between point resolution and functional density The long awaited chip from the first 3D run (now expected for beginning 2011) might provide useful information for the next submission Layout of the two pixel versions to start soon, submission expected for Q2 2011

16. Backup slides

17. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Deep N-well structure NMOS PMOS Buried N-type layer P-well Standard N-well P-substrate - + + + - - - - MAPS may satisfy the requirements (resolution, multiple scattering) of the experiments at the future high luminosity colliders DNW monolithic sensors were proposed to improve readout speed through sparsification techniques A DNW is used to collect the charge released in the substrate A classical readout channel for capacitive detectors is used for Q-V conversion  gain decoupled from electrode capacitance NMOS devices of the analog section are built in the deep N-well Using a large detector area, PMOS devices may be included in the front-end design  charge collection inefficiency depending on the ratio of the DNW area to the area of all the N-wells (deep and standard) DNW-MAPS

18. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Tezzaron vertical integration process Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Cu (M1 – M5) Cu (M6, Top Metal) “ Super-Contact ” Complete transistor fabrication on all wafer to be stacked Form super via (TSV) on all wafer to be stacked Fill super via at the same time connections are made to transistors

19. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Tezzaron vertical integration process Complete back end of line (BEOL) processing by adding Cu metal layers and top Cu metal Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Cu (M1 – M5) Cu (M6, Top Metal) “ Super-Contact ”

20. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Tezzaron vertical integration process Bond first layer to second layer using Cu-Cu thermo- compression bond

21. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Tezzaron vertical integration process Thin the second wafer to about 12 μm total thickness to expose super via Add Cu to back of second wafer to bond second wafer to third wafer OR add metallization on back of second wafer for bump bond or wire bond

22. L. Ratti, “Analog front-end for vertically integrated monolithic and hybrid pixels”, XV SuperB General Meeting Tezzaron vertical integration process 3σ alignment=1 μm, missing bond connections=0.1 PPM Via size plays an important role in high density pixel arrays Tezzaron can place vias very close together