1. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 1 Introduction Preparation FE-I4 Preparation FE-TC4-Proto Tests CPPM FE-I4-Proto Tests au PS CERN en 2009

2. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 2 Preparation FE-I4 IBL workshop 25-26 june, Bonn FE-I4 workshop 1-2 july, IBL kickoff 8 july juillet 2009 test de FE-I4-Proto2 et SEU-test3 au CPPM aout/septembre 2009 test de SEU-test3 au PS CERN aout-septembre 2009 soumision de FE-I4 A3 like cell into FE-I4 DAC pixel latch SEU latch library (VERILOG compatible) for EOC control SEU glitch protection of reset, load etc few columns with low consumption discriminator temperature/leakage ADC

3. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 3 Preparation FE-TC4 Optimisation transistors of Chartered Optimization of wire-bond pads (IBM like ?), buffers Latchup protection (special chip FE-C4-P2 ???) Simulation/crosscheck of the Bonn digital readout Feedback from irradiation on analog Feedback from SEU irradiation on digital, reset, load Compressing analog from 166 um to 125 um Resolving Vdd current problem (10-14 mA)

4. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 4 Resolving latchups FE-C4 IBM 130 nmChartered 130 nm R substrate10 16, 5-6 ohm cm 2 10 15, 6-9-12 ohm cm R p-well8 10 17 (boron)1 10 17 ????? R n-well1 10 17 (arsenic)1 10 17 ????? Distance n-well – n+??? Buried n+ inside p-wellyesYes ??? Low resistance contact of p-well to Gnd Low resistance contact of n-well to Vdd n+ gardring around n-wellpartial??? p+ gard ring around p-wellpartial???

5. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 5 Design FE-TC4 Chip size the 18.8 x 20.1 mm (336 rows x 160 columns, EOC 1.95 mm) Pixel pitch 50x125 um, bump bond pads compatible with 250 um sensor pitch keep the possibility of different flavors in some columns (on condition of safety for chip and good performance for modules) Pros: sensor compatible, bump bonding compatible, module/stave integration, testing tools, software, mechanics, reuse of FE-I4 blocks, 2 time more chips Cons: cost

6. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 6 Cost FE-TC4 Chip size the 18.8 x 20.1 mm = 378 mm2 Chartered reticule 26x31 mm= 806 mm2, usage 378/806=47 % Total run cost TC 350 k$ + tier2 masks 295k$= 645 k$ If multiproject => 645 k$ * 0.47 = 303 k$ Financing: 100kE (CPPM)+100kE(Bonn)+80kE(Vitesse)=280 kE=364k$ Additinal money: 200 k$ (FNAL+Italy+FranceILC)+20k (LBNL)+160k$(China)

7. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 7 Plan B:Design FE-TC4-Half Worste case: ugly, almost too late for IBL Chip size the 18.8 x 9.85 mm (336 rows x 78 columns, EOC 1.95 mm) Pixel pitch 50x125 um, bump bond pads compatible with 250 um sensor pitch gaps of 2*125um in z between chips in the module, big pixels on sensors Pros: low cost, sensor compatible, bump bonding compatible, module/stave integration, testing tools, software, mechanics, reuse of FE-I4 blocks Cons: gaps, special bump bonding tools, 2 times less chips

8. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 8 Plan B: Cost FE-TC4-half Chip size the 18.8 x 9.85 mm = 186 mm2 Chartered reticule 26x31 mm= 806 mm2, usage 186/(806/2)=46 % Total run cost TC 350 k$ If multiproject => 350 k$ * 0.46 = 161 k$ Financing: 100kE (CPPM)+100kE(Bonn)+80kE(Vitesse)=280 kE=364k$ We can do one run of FE-TC4-half without multiproject

9. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 9 Tests CPPM Test latchup without irradiation FE-C4-P1 Vdd=1.5->1.0->read/write- >Vdd=1.5v – june S-curves and Single transistors tests FE-C4-P1 – june-july Low consumption Discriminator test FE-C4-P1 – june/july Qualification test SEU3 – june/july S-curve test s FE-TC4-P1 - september Test setupBonn (carte USB Bonn, soft Bonn) when ??? Bump bonding IZM, thermal tests FE-TC4-P1 october-november (if money..)

10. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 10 Test au PS CERN 2009 Analog test FE-C4-P1 – june Single transistor tests FE-C4-P1 june/july SEU3 flipflop - august SEU2+SEU3 40 Mhz - august september Irradiation FE-TC4-P1 - october Irradiation X-ray CERN FE-TC4-P1 - october

11. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 11 Longer term prospective Test chip with LBNL on 90 nm/65nm in 2010 Small test chip for SLHC-phase2 b-layer FE-TC5-P1 25 -50 um transversal pitch (occupancy effect) 50-125 um longitudinal pitch architecture for L=10**35 correct buffers, no inefficiency, clustering, trigger 2 or 3 tiers ?

12. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 12 Budget 2009 Pas d’argent frais (10K)-> vider les relicat -> negative debut 2010 Delais robot a 2010 delais bump bonding IZM 2010 ??? Aide de Bonn pour FE-I4 de 100K, status d’organisateur ? Demande de 32K de reserve IN2P3/CERN

13. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 13 Budget 2010 Electronique – 179 K Mecanique – 67 K Exploitations pixel CERN – 5 K Informatique – 4K Fonctionnement CPPM -16 K Total - 267 K Pixel/SLHC missions – 65 K

14. Plans 2009/2010 CPPM 9 June 2009 A.Rozanov 14 Appendux

15. Plans 2009/2010 FE-I4_proto1 Participating institutes: Bonn, CPPM, Genova, LBNL, Nikhef. FE-I4-P1FE-I4-P1 LDO Regulator Charge Pump Current Reference DAC s Control Block Capacitance Measurement 3mm3mm 4mm4mm 61x14 array SEU test IC 4-LVDS Rx/Tx ShuLDO +tris t LVDS/LDO/10b- DAC 15 CPPM 9 June 2009 A.Rozanov

16. Plans 2009/2010 Analog tier In FE-I4_proto1 Preamp Amp2 FDAC TDAC Config Logic discri 50  m 145  m 16 CPPM 9 June 2009 A.Rozanov

17. Plans 2009/2010 Digital Readout Architecture FE-I3 bottleneck Both FE readout based on double column (DC) structureBoth FE readout based on double column (DC) structure FE-I4 local storage All hit pixels are shipped to EoC buffer. A hit pixel need to transfer its data to EoC before accepting new hit  congestion. Each pixel is logically independent inside the DC. Store data locally in DC until L1T. Only 0.25% of pixel hits are shipped to EoC  DC bus traffic “low”. Warning: Local Buffer Congestion??? Each pixel is tied to its neighbors -time info- (clustered nature of real hits). low traffic on DC bus 17 CPPM 9 June 2009 A.Rozanov