1. ADC 1 Analog to Digital Converter

2. ADC 2 ADC Features n General Features -Supports 8 or 10-bit resolution Modes, -Track period fully programmable up to 17 ADC clock cycles, -10 ADC clock cycles for a 8 or 10-bit conversion, -Up to 8 Analog inputs. n Triggering Mode -Software Mode, -By using an internal Counter/Timer output, -By using a specific application signal via a dedicated pin. n Running Mode -Sleep Mode, -One shot on Mono-Channel, -One shot on Multi-Channel, -Continuous Mode in Mono or Multi-Channel by using external triggering. n Processor-less transfer capability -Peripheral Data Controller (PDC).

3. ADC 3 View of the external ADC Signals n Analog Inputs -4 Analog inputs (AD4 up to AD7), -4 multiplexed lines between Analog and PIO (AD0 up to AD3), n Dedicated external trig input through ADTRG, n External Voltage Reference input through ADVREF.

4. ADC 4 Hardware consideration n The ADC is powered on VDDIN power rail, n ADx Impedance requirements: With a programmable track period (T track ), up to 17 ADC Clock cycles, the user can drive ADC input with impedance up to: -Z OUT <=(T track - 470) x 10 in 8-bit Mode, -Z OUT <=(T track - 589) x 7.69 in 10-bit Mode, With: T Track expressed in ns, Z OUT expressed in Ohms.

5. ADC 5 How to start conversions ? ADC_CR (Control Register) START TIOA Channel 0 Rising edge on ADTRG pin TRGSEL Field ADC_MR (Mode Register) TRGEN TRGSEL 0 1 2 3 TRGEN Bit 1 TIOA Channel 1 0 Software Trig Hardware Trig ADC Trig Input

6. ADC 6 How to valid Mono/Multi-Channel Conversion n After one start event, the ADC start -one analog to digital conversion on the enabled channel by the user via the ADC_CHER register => Mono-channel Conversion, -successive analog to digital conversions on the enabled channels by the user via the ADC_CHER register => Multi-channel Conversion, 0 CH [0 to 7] 7 ADC_CHER(Channel Enable Register)

7. ADC 7 Can I perform Continuous Conversions ? n With a continuous trigger source, the ADC will perform continuous conversions: -With the Timer/Counter as trigger source: As soon as AND As long as the Timer/Counter is triggered, conversions are started at defined sampling rate In Mono-channel mode, In Multi-channel mode. -With the dedicated trig input pin: As soon as AND As long as there are rising edge on the ADC’s trigger input pin, Free-conversion are started In Mono-channel mode, In Multi-channel mode.

8. ADC 8 Power-up, Reset and Sleep Mode n After a Power-up or a hardware or software reset, the ADC Clock is enabled at PMC level by default: -The ADC is in Sleep Mode: Low Power Mode, -Get out from the Sleep mode requires a Startup Time. The user will have to set the STARTUP field according to the data in electrical datasheet (20 µs min) ADC_MR (Mode Register) 16 18 0171920 STARTUP Field n The SLEEP bit in ADC_MR Register -Enable the low power mode between each conversion (reduce current consumption from 1mA down to 1µA), -But, the ADC will start the next ADC conversion after the necessary wake up time defined in STARTUP field as after power-up or reset. 5 SLEEP

9. ADC 9 Software Reset bit: SWRST n It is possible to complete a reset at ADC level by using the dedicated SWRST bit in ADC Control register. n Set the SWRST bit act on: -The ADC registers will be set with their default values, -The ADC will be in SLEEP mode. ADC_CR (Control Register) SWRST 1 0

10. ADC 10 Set up the ADC in your Application Reset State Set up the ADC parameters Enable the required Channel n Initial State or Software Reset at ADC_CR register level n Set up the following parameters through the ADC_CR register - Track Period for the sampling, - Startup Time of the ADC, - Clock Frequency of the ADC, - Enable or Disable the Sleep Mode, - Select the 8 or 10-bit resolution Mode, - Select between Software or Hardware trigger sources, - Select the hardware source of the trigger (between Timer/Counter or external signal) n Use the ADC_CHER register in order to enable the channel required by the application. The ADC is now ready to start conversions

11. ADC 11 Read Method: Polling Mode n Polling Method -Firstly wait the read condition: EOC In mono-channel mode, read the respective End Of Conversion status bit according to the enabled Channel, In Multi-Channel mode, read the End Of Conversion status bit from the last converted channel. -Secondly read conversion result(s) In mono-channel mode, read the respective Channel Data Register or the Last Data Converter Register, In multi-channel mode, read the X results from each X Channel Data Registers according to the X enabled channels. ADC_LDCR ADC_CDR0 ADC_CDR7 ………… Contains the Last Converter Result A D AD0 AD7 … Each channel has its own result register

12. ADC 12 Read Method: Interrupt Mode ADC_SR (Status Register) 16 18 01719317 EOC [0 to 7] n Interrupt Method after an End Of Conversion -An interrupt can be independently enabled for each EOC status bit ADC_IER (Interrupt Enable Register) 16 18 01719317 EOC [0 to 7] n Method for application using multi-channel conversion: The EOC of the last converted channel should be used to start the read interrupt sub-routine in order to be sure the previous channel have been converted too.

13. ADC 13 Prevention about Overrunning n The user can be warn about overrunning -Do not read a data in a channel before the next conversion on the same channel will set the dedicated overrunning status bit in Status Register ADC_SR(Status Register) 16 18 01719317 OVRE[0 to 7] 815 n Interrupt Capability -The user can enable an interrupt when one of OVRE Status bit rises ADC_IER(Interrupt Enable Register) 16 18 0171719317 OVRE[0 to 7] 815

14. ADC 14 Typical Result Read End Of Conversion (polling or interrupt method) Read the channel conversion result Read the dedicated overrun bit ADC_SR (Status Register) 0 1 8 or 10-bit Conversion result Field 0 1 ADC_CDRx (Channel Data Register for the x channel) EOC0EOC1EOC7 7 9 8 9 OVR0OVR1OVR7 15 ADC_SR (Status Register) 8-bit Mode 10-bit Mode

15. ADC 15 Processor-less Transfer Capability n All previous running modes described are still possible with the processor in Idle Mode -ARM7TDMI ’s Clock stopped, -ADC results transfer from ADC to memory via PDC. n How to read PDC data buffer after a full transfer with -P valid channel, -N valid conversion

16. ADC 16 Memory Map of a PDC Data Buffer n Input data example: -2 enabled channels CH0 and CH1, -ADC set in 10-bit Conversion Mode, -PDC Counter set to 64 transfers for 32 targeted samples for each channel. x x + 1 CH0, data[0] CH1, data[1] CH0, data[2] CH1, data[3] CH1, data[63] x + 2 x + 3 x + 63 X is the Base Address of the PDC buffer Y is the Data Counter of the PDC 64 63 62 61 0 n General rules to start this process -Set the ADC in 10-bit Mode set automatically the PDC in 16-bit transfer mode, -The PDC counter (Y in this example) shall be equal to [number of valid channels] x [number of samples by channel]. … 16-bit size n Result after completed transfer -Interleaving ADC results in PDC Memory Buffer

17. ADC 17 PDC Status and Interrupt n 2 Dedicated Status Bit for the ADC’s PDC ADC_SR(Status Register) 16 18 17193115 ENDRXRXBUFF Both, Receive Counter Register and Receive Next Counter Register have a value of 0. The Receive Counter Register has reached 0 since the last write in Receive Counter register or Receive Next Counter register (when the application uses dual buffers). ADC_IER(Interrupt Enable Register) 16 18 17193115 ENDRXRXBUFF n PDC ‘s events can act on the system via dedicated interrupt

18. ADC 18 Last Converter Data Register and PDC New Result in ADC_LCDR set the DRDY Status bit ADC_SR(Status Register) 16 18 17 GOVRE ADC_SR(Status Register) 15 17 16 DRDY Two successive results in ADC_LCDR without previous read set the GOVRE Status Bit A D ADC_LCDR A D 2 successive conversions without any previous ADC_LCDR read by the PDC n The PDC uses the Last Converter Data Register to transfer Converter result to the PDC ’s RAM buffer. n The user can be warned after any overrun case when the PDC is running

19. ADC 19 Timing: Why, Compute, Constraint Necessary ADC Startup Time Track periodConvertion Time Depends on intrinsic ADC characteristic Depends on the highest user’s driver impedance connected on ADC’s input ADC_MR (Mode Register) 1620 STARTUP Field SHTIM Field 2427813 PRESCALER Field In all cases, must be the lowest time with the SLEEP Mode enabled 8(STARTUP+1)/ADCClock (SHTIM+1)/ADCClock MCK/(2(PRESCALER+1)) Min. = 20 µs Z OUT <=(T track - 470) x 10 (in 8-bit Mode), Z OUT <=(T track - 589) x 7.69 (in 10-bit Mode), Z OUT <=(T track - 470) x 10 (in 8-bit Mode), Z OUT <=(T track - 589) x 7.69 (in 10-bit Mode), ADC Clock cannot be upper than 5 MHz

20. ADC 20 Current Consumption Consideration - After a power-up, a reset and before the first conversion, - Or, between conversion processes with the SLEEP mode enabled. - In convertion process, - Or, between conversion processes with the SLEEP Mode disabled. 1 µA 1 mA n The ADC is an analog Cell: Continuous bias currents are major current consumption. The lowest conversion time between the SLEEP Mode State results in the lowest current consumption average.