2. S.O.I. (SILICON ON INSULATOR) PRESENTED BY: ARUN KUMAR PANDEY PREETAM KUMAR

3. INTRODUCTION WHAT IS SOI ? WHY SILICON ON INSULATORS ? FABRICATION OF SOI MECHANISM OF SOI TYPES OF SOI FDSOI PDSOI FDSOI v/s PDSOI EXPERIMENTS WITH SOI ADVANTAGES OF SOI TECHNOLOGY DISADVANTAGES OF SOI TECHNOLOGY APPLICATION OF SIO TECHNOLOGY SOI -POWER DISSIPATION SCALING & COST INDUSTRIAL NEEDS USE IN MICROELECTRONICS INDUSTRY SOI CHIP v/s CMOS CHIP CONCLUSION AND FUTURE WORK REFERENCES CONTENTS

4. INTRODUCTION: Latest fabrication technology. Chip in a Blanket. Silicon-on-Silicon. Increasing demand for high performance, low power & low area among micro-electronic device led to its invention.

5. INVENTION:  SOI (silicon-on-insulator) has been known for ~ 20 years.  In 1993 Honeywell started product development of SOI to support commercial aircraft electronic engine controls.  First it was used for military purposes in U.S.A.

6. What is ?  It is the latest fabrication technique.  It is easier & cheaper.  Transistors are build on a silicon layer resting on insulating layer of silicon-di-oxide known as BOX (burried oxide).  Only a thin layer from a face of the wafer used for making electronic components, the rest essentially serves as mechanical support. S.O.I.

7. WHY ?  To enhance the performance.  H Higher speed.  Less power consumption.  Easier fabrication.  Cheaper etching process.  M More electronic devices can be fabricated on same chip (30% more than bulk).  It reduces parasitic capacitance when compared to bulk or epi-wafers. S.O.I.

8. FABRICATION OF ?  Fewer mask and ion implementation steps (because of the elimination of well & field isolation implements).  Less complex (costly) lithography and etching required to achieve next-generation performance.  Some fabrication process:  SIMOX – Separation by Implantation of Oxygen  Smart-cut SOI Technology  BESOI – Bond and Etch-back SOI  SOS – Silicon-on-Sapphire S.O.I.

9. SIMOX ( Separation by Implantation of Oxygen):  High temperature Annealing process is used.  Right dose of oxygen is implemented on Si to form SiO 2.  Ion Impementation technique (Ion of a material are accelerated in an electric field and impact into the other solid is called Ion Impementation technique) is used.

10. Smart-cut SOI Technology :  The Smart Cut process was developed and is patented by SOITEC corporation from France.  Technological Process that enables the transfer of very fine layers of crystalline material onto a Mechanical Support.

11. BESOI – (Bond and Etch-back SOI):  It is the technique of fabrication of semiconductor device or interconnection of electronic device to form desired circuit.  It is done after formation of SOI wafer.

12. SOS – (Silicon-on-Sapphire):  It is a part of SOI family of CMOS technique.  In this process layer of silicon is grown on sapphire (Al 2 O 3 ).  It is a hetero-epitaxial process

13. HOW IT IS... FASTER ( 20% to 35% than BULK ) ? CONSUME LESS POWER ( 35% to 70% then BULK ) ? DENSER FABRICATION ( due to better isolation property ) ? CHEAPER FABRICATION METHOD ( due to cheaper etching process ) ? BULK S.O.I.

14. 1.Charge collection decreases significantly in SOI device. BULK

15. 2. Low junction capacitance (Hence less power dissipation). T SOI BULK S.O.I.

16. 3. Better isolation lets denser fabrication: It is recognized by IBM that 30% more electronic devices than those of bulk can be fabricated in SOI. 4. Latch up Elimination: SOI has no wells into the substrate and therefore no latch up or leakage path.

17. 5. Self heating:  SOI wafer creates a potential temperature delta between device called local heating or self heating. This happens only when there is logic switching in the device.  It has less impact on digital circuit but huge impact on analog circuit. 6. False switching:  A low gain parasitic bipolar transistor on every floating body SOI FET transistors.  Bipolar transistor is in parallel with the FET transistor and can cause false switching to the off FET transistor.  Over the years of the technology scaling, this bipolar current effect has been pretty much eliminated due to the reduction of the operating voltage of the 90nm node and beyond.

18. SOI device delay SOI results in at least 30% lower delay compared to bulk. SOI Power dissipation SOI results in about 70% lower power for the same speed. Scaling with SOI S.O.I. v/s BULK

19. TYPES OF S.O.I.: 1. Partially Depleted SOI(PD-SOI):  Silicon dioxide layer is thicker  History dependent Where, Tsoi = thickness of insulator Wt= width of substrate  The exact voltage depends on the history of source, gate, and drain voltages leading up to the current time (the “history effect”). SOI PD-SOI (Partially Depleted- SOI) FD-SOI (Fully Depleted-SOI)

20. 2. Planer Fully Depleted SOI: Silicon Substrate SourceDrain SiO 2 SOI Gate  FD-SOI technology relies on an ultra- thin layer of silicon over a Buried Oxide (commonly called BOX). Where, Tsoi = thickness of insulator Wt= width of substrate  History independent 

21. History Effect In PD—SOI: Input Output First switch Second switch 1.In PD—SOI the next switching time marginally depends on previous switching time 2.The second switch is seen to be faster than the first switch This is known as ‘History Effect’. Floating body effect:  Usually seen in Partially-Depleted S.O.I.  As shown in figure, the MOS structure is accompanied by a parasitic bipolar device in parallel.  The base of this device is ‘floating’.

22. Fig.: Differentiating BULK Devices from PD-SOI & FD-SOI:

23. Experiments with S.O.I.: Results: Iron  Small amount of tiny pits are seen Result: Molybdenum  No or negligible tiny pits are seen Results: Nickel  Smaller amount of tiny pits are seen Characteristics of defects created on “silicon on insulator” (SOI) wafers by each of various contaminants, specifically iron, nickel, and molybdenum.

24. ADVANTAGES Of S.O.I. :  Suitable for high-energy radiation environments.  Parasitic capacitances of SOI devices are much smaller.  No latch-up.

25. ADVANTAGES (contd..):  Elemination of Substrate Noise  Less Temperature Sensitivity

26. ADVANTAGES (contd..):  Easier device isolation.  High device density.  Easier scale-down of threshold voltage.  SOI technology is useful for implementing high-speed op-amps – given its low Voltage.  Higher transconductance (especially of FD) implies higher gain.  Lower power consumption compared to bulk devices at low current level.  Easier device isolation.  High device density.  Easier scale-down of threshold voltage.  SOI technology is useful for implementing high-speed op-amps – given its low Voltage.  Higher transconductance (especially of FD) implies higher gain.  Lower power consumption compared to bulk devices at low current level.

27. ADVANTAGES (contd..):  Uses in digital and analog circuits  A combination of FD and PD devices are used in digital circuitry.  Used for making SIO CHIPS  Superior capabilities of SOI CMOS technology – usage in memory cell implementation.  Uses in digital and analog circuits  A combination of FD and PD devices are used in digital circuitry.  Used for making SIO CHIPS  Superior capabilities of SOI CMOS technology – usage in memory cell implementation.

28. LIMITATIONS OF S.O.I. :  Major bottleneck is high manufacturing costs of the wafer.  Floating-body effects impede extensive usage of SOI.  Floating body causes the History Effect Self-heating

29. APPLICATIONs. Daily use product such as markets such as : Mobile Internet Devices (Smartphones, Tablets, Netbooks …), Imaging (Digital Camera, Camcorders…), Cellular Telecom, Mobile Multimedia, Home Multimedia (Set Top Box, TV, Blu-Ray), Automotive Infotainment, etc. Broadband Modems Digital Camera

30. SOI Wafer Classificatio n on (BOX) BOX Thickness, in Microns System Level Application IC Type Key System Requirement Ultra-thin< 0.15High End PCsMPUHigh Speed Ultra-thin< 0.15ServersMPUHigh Speed Thin0.15 to 1WorkstationASIC – Logic High Speed/Small Die Thin0.15 to 1Handsets/PDAMixed Signal Low Voltage/Power Thin0.15 to 1MainframesHigh End LogicHigh Speed Thin0.15 to 1 Portable “Wireless” RF/IF trans/rec Low Voltage/Power Thin0.15 to 1AutomotiveMixed SignalHigh Power Thin0.15 to 1 Consumer – Digital ASIC – Logic Low Voltage/Power Thick0.5 to 5 Military/Aeros pace RF/IF trans/rec Radiation Hardened Thick0.5 to 5IndustrialBipolar, Power IC’s High Power Applications according to thickness :

31.  We have investigated the SOI technology and its application to next generation low power, high performance DRAM systems by intensive simulations.  Our experimental results show that SOI can reduce the C b /C s ratio significantly which implies either further Cs reduction or lower operation voltage.  Due to its characteristics, SOI is fast becoming a standard in IC fabrication.  Several companies have taken up SOI manufacturing.  High-volume production of SOI is yet to become common. Conclusion AND FUTURE WORK:

32. References:  J.P. Colinge, “Silicon-On-Insulator Technology: Materials to VLSI, Second Edition”  D. K. Sadana and M. Current, “Fabrication of Silicon-On- Insulator (SOI) Wafers Using Ion Implantation”.  J. Kuo, Low- Voltage SOI CMOS VLSI Devices and Circuits.  http://www.seminarprojects.com http://www.seminarprojects.com  http://en.wikipedia.org/wiki/silicononinsulatorhttp://en.wikipedia.org/wiki/silicononinsulator  http://www.jpl.nasa.gov http://www.jpl.nasa.gov  http://www.google.com http://www.google.com