1. SKIROC status CERN – CALICE/EUDET electronic & DAQ meeting – 22/03/2007 Presented by Julien Fleury

2. Common DAQ Slice FE FPGA PHY VFE ASIC Dat a Clock+Config+Control VFE ASIC VFE ASIC VFE ASIC Conf/ Clock - Timing is the same for all detectors - Number of channels involves embedded electronic for all detectors -Outputting of data is done the same way for all detectors  Back-end of very-front-end shall be common for all detectors VFE AsicFE electronicDetector FE of VFE BE of VFE Concentrator

3. Time considerations time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 us) Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% duty cycle 199ms (99%) analog detectors only

4. Read out : token ring Acquisition A/D conv.DAQIDLE MODE Chip 0 Chip 1 Acquisition A/D conv.DAQIDLE MODEIDLE Chip 2 Acquisition A/D conv.IDLE MODEIDLE Chip 3 Acquisition A/D conv.IDLE MODEIDLE Chip 4 Acquisition A/D conv.IDLE MODEIDLEDAQ Chip 0Chip 1Chip 2Chip 3Chip 4 5 events3 events 0 event 1 event 0 event Data bus

5. Acquisition mode  No time measurement  Synchronous hold validated by internal trigger BCID NN+1N+2 Trig OR Trigger_validb Hold Machine sync. Hold Peaking time Valid_hold (analogue memory address) kkk+1

6. SKIROC presentation - ECAL read out - Silicon PIN detector - 36 channels -Compatible new DAQ

7. Main features  Designed for 5*5 mm² pads  36 channels (instead of 72 to reduce cost of prototype)  Detector AC/DC coupled  Auto-trigger MIP/noise ratio on trigger channel : 16  2 gains / 12 bit ADC  2000 MIP Energy resolution :4.89 GeV @90° (cf JCB) MIP/noise ratio : 11  Power pulsing Programmable stage by stage  Calibration injection capacitance  Embedded bandgap for references  Embedded DAC for trig threshold  Compatible with physic proto DAQ Serial analogue output External “force trigger”  Probe bus for debug  24 bits Bunch Crossing ID  SRAM with data formatting  Output & control with daisy-chain Digital on FPGA for debug

8. One channel

9. Digital

10. Block scheme of SKIROC Ch. 0 Ch. 1 Analog channel Analog mem. 36-channel Wilkinson ADC Analog channel Analog mem. Ch. 35 Analog channel Analog mem. Bunch crossing 24 bit counter Time digital mem. Event builder Memory pointer Trigger control Main Memory SRAM Com module ECAL SLAB

11. SKIROC : RAM Mapping Charge Measurement 185 15 0..................... 0 5 5x36 Time stamp (BCID) Chip ID (8 bits) 0 0 0 0 0 7 Time stamp (12 bits) ADC measurement (12 bits) Gain (1 bit) Hit (1 bit) Time stamp (12 bits) ADC measurement (12 bits)

12. STATUS  Chips are due this month MPW delayed by a couple of weeks  Testboard is in fab 5 PCBs are due for next week Assembling in house Firmware is in developpment Labview software is in development  First results for the next CALICE meeting  Some more at LCWS