1. Update on works with SiPMs at Pisa Matteo Morrocchi

2. - Test of front-end electronics - Test of ASICs - Electronic contribution at timing - Tests of SiPMs, single and integrated in arrays. - SiPM characterization - Timing performances - Development of system for ASIC Read-Out - Development of system for ASIC management H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n ACTIVITIES

3. 32-Channels Front-End chip developed at the Politecnico of Bari in the INFN experiment DaSiPM2[1]: [1] C. Marzocca, BASIC32: development of a multichannel readout ASIC for SiPM detectors, 8th International Meeting on Front-End Electronics, May 24-27 2011 Bergamo SiPM signal is replicated by a Front-End buffer and splitted in two branches Charge Amplifier and Peak Detector to measure the energy of the event using 3 different gains and 3 different integration windows. Fast discriminator for timing information: external trigger is obtained by the OR logic of the 32 triggers. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n BASIC 32 CHIP – ANALOG

4. C = 1000 pF C = 390 pF Charge (pC) Standard deviation (ps) Characterization of the timing performances of the Fast-OR logic using an 8-channels version of the BASIC chip implementing the same architecture for trigger. Electronic contribution has been evaluated using test signals. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n ASIC CHARACTERIZATION

5. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n TRIGGER LEVELS MEASUREMENT OF THRESHOLD LEVELS FOR THE CURRENT DISCRIMINATOR Counts measurements in function of the test signals amplitude: LevelThreshold (μA) 0304 ± 5 1399 ± 6 2491 ± 7 3563 ± 8 4622 ± 8 5747 ± 10 6829 ± 12 7918 ± 10 Counts (norm.) Current (uA) d counts / d current Threshold Current (uA)

6. Matrix FBK-Irst: ASD-SiPM4S-P-4×4T-50 Dark Counts:4.5·10 7 ÷ 8·10 7 Cells number:6400 Cell size:50 um x 50 um SiPMs active area:4 x 4 mm 2 Pitch:4,7 x 5,0 mm 2 H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n SiPM MATRICES

7. Xilinx ML605 FPGA Evaluation Board (Virtex 6) GIGAbit Ethernet communication with host computer Two Boards host the Front-End electronic. Each board contains a 32- channels ASIC and ADCs. One board is connected to the module, all the 32 channels are used, the other board is connected to a single SiPM for coincidences. A LabVIEW interface manages the communication with the board, the bias voltage of the tiles, the settings of the ASICs Temperature control of the matrices at 20° C THE READ-OUT H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n

8. Gain calibration of the single SiPMs of the two tiles using the signal of a laser and irradiating one pixel for each acquisition. LUT for amplitude correction of the signal of each SiPM. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n GAIN CALIBRATION

9. GAIN AND NOISE H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n The gain and the noise dependence on the break-down voltage have been analyzed for the two tiles, using these plots, the best point in terms of signal to noise ratio can be obtained

10. PIXELLATED CRYSTALCONTINUOUS CRYSTAL ACQUISITION IN COINCIDENCE WITH SINGLE PIXEL H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n ACQUISITION WITH 22Na SOURCE -Higher Energy resolution due to the collection of the light in a single device - Spatial resolution limited by the pitch of the matrix. -Lower Energy resolution, due to the sharing of the light between SiPMs and dead areas - Spatial resolution higher but dependent on the position in the tile

11. 64 Channel matrix sharing a common silicon substrate: - 840 microcells per SiPM - Active area:1,3 x 1,5 mm 2 - Pitch:1,5 x 1,5 mm 2 - Bias Voltage: about 30 V* * Bias Voltage is common to all the matrix but several tests have demonstrated a high uniformity in the break- down voltage of the pixels sharing the same substrate. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n MONOLYTHIC MATRIX

12. V bias 31,3 V31,5 V31,7 V En. Res. (%)19,8 ± 0,715,3 ± 0,416,6 ± 0,5 31,3 V 31,5 V 31,7 V Energy resolution with different bias voltages of the SiPM matrices coupled one to one to a LYSO array of 10 mm thickness. Counts Channel Counts Channel H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n ENERGY RESOLUTION

13. σ = 0,77 ± 0,03 ns σ = 0,84 ± 0,04 ns Coincidence between two lines of the matrices with 22 Na Digital signals sent to the scope: band-width 1,5 GHz sampling of 2 GS/s 1 V overvoltage 0,5 V overvoltage Delay (ns) Occurrence H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n TIMING PERFORMANCES

14. Th. 0 Th. 1Th. 2 σ th0 = 550 ± 20 ps σ th1 = 740 ± 20 ps σ th2 = 1950 ± 20 ps Hamamatsu SiPM 3 x 3 mm 2 coupeld with LYSO 3 x 3 x 10 mm 3 MEASUREMENT OF THE TIME DISTRIBUTION OF THE COINCIDENCE EVENTS Standard deviation(ns) Threshold Voltage (mV) Results comprehend the electronic contribution because timing is obtained with Fast-Or signals of two DAQs H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n TIME RESOLUTION OF SiPM + LYSO CRYSTAL

15. Time distribution of the coincidence using two 3x3mm 2 Hamamatsu SiPM coupling to two 3x3x10mm 3 LYSO crystal using 22Na source (only peak events considered). TIMING MEASUREMENT H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n

16. TIMING MEASUREMENT WITH LASER H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n FWHM = 106 ps Timing acquisition with laser source at three different thresholds in standard conformation and inverting anode and cathode

17. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n SYSTEM DEVELOPMENT Requests Creation of an acquisition system based on BASIC32 with the following features: At least 128 analog read-out channels Possibilities to trigger the reading with an external input. TDC at high and low resolution implemented in the FPGA. Capabilities to manage the configuration and calibration of the system. Possibility to extend the system to 256 analog channels. The development of the system is executed as a collaboration between Pisa and Perugia

18. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n SYSTEM DEVELOPMENT The structure The system is composed of a motherboard and some boards that host the Front-End electronics. The communication between boards and motherboard is implemented with LVDS signals; a Patch Card to tranform LVDS signals in simple single-ended signals is therefore needed. The system structure allows to choose the number of boards to be connected.

19. H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n SYSTEM DEVELOPMENT SLOT FOR PATCH - BOARD ENTRIES FOR FAST-OR FPGA

20. HR - TDC H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n In Perugia a HR-TDC to collect temporal information on the delay between the Fast-Ors has been programmed. The TDC is implemented in the FPGA Stratix III located in motherboard. The signals generated by the Fast-or are compared with a Delay Line and a Look up table. The HR-TDC is not used to evaluate the coincidence but just to write the temporal information in the data. The coincidence is evaluated by a LR-TDC working at steps of 1.5- 2.5 ns. The HR-TDC is programmed in the FPGA, so: It’s related to the specific path in the board used for Fast-Ors. It has to be updated according to the number of Basic – Boards connected to the motherboard

21. 0 ns- 4 ns + 4 ns Example of timing distribution (10 ps per bin) obtained at 3 different time intervals between two signals generated by a pulse-generator. Missed Events HR - TDC H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n

22. FURTHER DEVELOPMENTS H a d r o n P h y s i c s 3 – S t a t e o f t h e a r t o f t h e I N F N P i s a c o n t r i b u t i o n