1. ASIC Development for Future Experiments Henrik von der Lippe LBNL

2. General Outline Introduction A glance at the current ITRS roadmap for analog Some 65nm device test results Some examples of current projects FEI4 (ATLAS) ATPIX65 (LBNL) MAPS (LBNL) HIPPO (LBNL) Conclusions

3. Introduction Performance and functionality of integrated circuits continued to increase over the past few decades. Technology scaling (down) has fueled what is known as Moore’s law (or is it vice versa?): the number of components per chip roughly doubles every 24 months. Transistor dimensions (width, length and gate thickness) are continuously decreased and so are the metal pitch while the number of metal levels has been increased. Process optimization for some niche market (like RF) has also led to multi-threshold and multi-supply transistors along with high quality passives.

4. Introduction While scaling down is still going on, industry experts are already introducing the concept of “more than Moore” to prevent the increase of performance of ICs from slowing down (physical scaling down will ultimately be unpractical). Without the advances in IC technology, some important HEP projects (at some crucial time) would not have been feasible or would have required specialized low yield, low performance, high cost processes. The future will be no different. Complex and challenging instrumentation projects (Upgrades, SLHS, new Detector concepts) will require the adoption of the ever more empowering (and more complex) IC technologies. This is exemplified by recent design activities using the 65nm CMOS node, which is the state of the art for this community. This talk will briefly describe some of the prototyping work in 65nm CMOS (mainly).

5. Industry and HEP IC “nodes” A.Baschirotto, University of Milano-Bicocca “LV Analog Design in scaled CMOS technology” (image without the HEP figures) 250nm, 70Mrad special layout 130nm, 250M`rad 65nm, >200Mrad HEP projects, even though lagging mainstream technology, are benefitting from Technology scaling. There should be a “topical” Moore’s law. ICs are only one part of an instrumentation system! Is detector technology keeping pace? 5

6. ITRS performance RF/Analog roadmap Year of Production  2009201020112012201320142015201620172018201920202021 Supply voltage (V)1.11.05 10.95 0.85 0.75 Tox (nm)1.2 1.10 1.00 0.90 Gate Length (nm)38 3229272218171514131211 gm/gds at 5·Lmin-digital30 1/f-noise (µV²·µm²/Hz)100908070 6050 40 30 s Vth matching (mV·µm)5555555555544 Ids (µA/µm)9987765443332 Peak Ft (GHz)240 280310340400480520570630680750820 Peak Fmax (GHz)290 3403804205106106707408209009901090 NFmin (dB)0.2<0.2 Notice difference between Performance versus precision (next slide) ITRS key: Yellow=solution known but not optimized. Red= solution not known. http://www.itrs.net/ 6

7. ITRS Precision Analog/RF roadmap Year of Production  2009201020112012201320142015201620172018201920202021 Supply voltage (V)2.51.8 1.5 Tox (nm)53333333332.6 Gate Length (nm)250180 130 gm/gds at 10·Lmin-digital220160 110 1/f Noise (µV²·µm²/Hz)1000360 270 s Vth matching (mV·µm)9666666666555 Peak Ft (GHz)4050 70 Peak Fmax (GHz)7090 120  Tox decreasing: better ionizing radiation resistance. Gate rupture? Other problems?  Gm/gds decreasing: Lower gain  1/f noise decreasing.  Matching improving (barely and only for analog devices)  Speed increasing  Supply voltage decreasing: reduced Dynamic range.  Other: gate leakage, off current, variability of non analog transistors … 7

8. The main design challenges (some) 8 Gate leakageBig problem biasing/controlling large number of transistors in parallel (pixels). Current is proportional to gate area: can be problematic for low noise large cap FENDs (wide input transistor) Be aware of the problem. Can be serious. Realistic simulations is a must. Design bias DACs to handle the excess current. Use higher voltage devices, if possible (be aware of radiation issues). Off leakage current Problem for low current circuits. May lead to higher power (increase operating currents to dwarf leakage) Use low leakage transistor variants (order of magnitude lower). Creatively live with it. Low Supply voltage Reduced Dynamic range. May lead to higher analog power. Problem for high precision/accuracy systems Use rail to rail circuits. LV circuits techniques… Highly layout dependent device parameters Makes design more complex. Requires a high quality design kit Read the manuals (obvious but …). Check the effects are back annotated for simulations. It is only a problem of degree. Analog design has always been about designing working circuits using imperfect devices. Good circuits were designed in NMOS only, single metal, single poly processes! Read IEEE JSSC!

9. ITRS bipolar Roadmap Year of Production2009201020112012201320142015201620172018201920202021 1/f-noise (µV²·µm²/Hz)21.5 111111111 s current matching (%·µm)2222222222222 High Speed NPN (HS NPN) - Common to mmWave Table Emitter width (nm)13012011010595908580757065 60 Peak fT (GHz)265285305325345365385405425445465485505 Peak fMAX (GHz)310350390430470510550590630670710750790 Maximum Available Gain (dB) @ 60 GHz 12.012.913.614.315.015.616.116.617.117.518.018.418.7 Maximum Available Gain (dB) @ 94 GHz 8.08.99.610.311.011.612.112.613.113.514.014.414.7 BVCEO (V)1.7 1.6 1.5 1.4 1.3 1.2 High Speed PNP (HS PNP) Emitter width (nm)500 300 200 150 Peak fT (GHz)254060808595105115125135145155165 Peak fMAX (GHz)4050809095105115130140150160170180 BVCEO (V)5.54.03.02.52.22.01.91.81.71.61.51.4 For specialized projects. Main challenge: breakdown voltage getting lower. 9

10. Advanced IC processes are available thru brokers TSMC CMOS (mosis) IBM CMOS (mosis) 10 VDD

11. Advanced IC processes available thru brokers IBM BiCMOS SiGe (MOSIS) St Micro CMOS (CMP) Other less advanced and specialized processes are available thru mosis, cmp, europractice And others! http://www.mosis.com http://cmp.imag.fr/ http://www.europractice-ic.com/ 11

12. Area reduction mostly for digital systems For analog design, most of the challenges can be addressed by proper device selection and design. But at the expense of increased area: Reduce analog functionality to the minimum to benefit from the ever increasing integration density in advanced process. Analog “deficiencies” can be mitigated by special digital techniques. Die area reduction based on analog/digital mix (A. Baschirotto ) 12

13. Harnessing digital processing power (a physicist perspective) 13  Complex pattern recognition on chip  Cluster formation, including NN-style.  Rejection of background clusters- eg. from beam halo particles  Generic user-programmable DSP  Pulse shape analysis.  Digital corrections for anything and everything (eg. Time-walk).  Self-repairing or self-testing designs. Either 100% yield or chips that automatically report their quality upon power-up (second probably easier)  Self calibrating, self timing-in, etc.  No need to save and download threshold tunes, for example, because threshold is automatically tuned on-chip in real time.  Automating monitoring, interlocking, etc.  Configurable geometry. Not all pixels have to be used. User selects desired density lower density = lower power and greater bump bonding pitch  Prompt hit processing (complex and fast processing of hits from pixel columns) M. Garcia-Sciveres, Atlas Upgrade Week 11/16/11

14. Illustration of the Power of integration >One 32bit ARM11 processor core Per 4 columns (65LP)! Fits in the dead area! FEI4: 0.13  ATLAS Pixel ROC ~ 20mm X 20mm Size would probably remain the same if implemented in 65 nm FEI4: 0.13  ATLAS Pixel ROC ~ 20mm X 20mm Size would probably remain the same if implemented in 65 nm 14

15. 65nm: Some transistor test result M. Manghisoni et al. TWEPP 2011 Same gate capacitance  No noise degradation at lower nodes  No thermal noise increase with radiation  No or little 1/f noise increase with radiation 15

16. 65nm: Some radiation tolerance results Threshold voltageLeakage current S. Bonacini et al. TWEPP 2011 65 nm devices seem to outperform their 130nm counterparts in their tolerance to ionizing radiation ! 16

17. Example 1: FEI4A (ATLAS PIXELS FOR IBL) FEI4A 0.13u process Performs also most of a module Controller chip duties FEI3 0.25u process  Copes with higher hit rate: regional architecture and smaller pixel size  Improved cost effectiveness: Large chip with large active area  Lower power: Improved design and architecture  Increased radiation tolerance (~250Mrad) 17

18. FEI4 (cont’d) Column drain architecture (a la FEI3) saturates at high rate – All pixel hits are sent to periphery – Column based readout induces dead-time (during data transfer to periphery and column readout) ATLAS solutions for higher rate → Development of regional architecture in FEI4 enabled by migration to a finer process 18

19. FEI4 PIXEL REGION FEI4 is organized in digital regions serving 4 analog pixels Hits are stored locally during L1 latency – 5 ToT memories per pixel, 5 latency counters per region Hits are not moved unless triggered – only 0.25% of hits are sent to periphery Lower digital power consumption (6μW/pixel at IBL occupancy) 19

20. FEI4: Pixel front end Similar design of analog pixel in FEI3/FEI4 Two-stage amplification Clock is distributed to all digital pixel region ToT counters within pixel digital region ToT together with pixel address sent to periphery 20

21. FEI4A: A result 1500 2000 2500 3000 3500 4000 5000 10 3 10 2 10 1 10 -1 Constant 849 Mean 3178 Sigma 403 2700 2900 3100 3300 3500 10 3 10 2 10 1 10 -1 Constant 2865 Mean 3100 Sigma 26 FEI4 bump-bonded to planar and 3D sensors have been successfully operated in lab test, test beams and cosmic data taking Tuned threshold dispersion ~30e FEI4 low threshold operation (~700e) shows promising results with reasonable dispersion Irradiation tests with bare chips show no effect on threshold dispersion and 20% increase in noise Threshold tuning at 1400e Threshold [e] before tuning after tuning 21

22. Example 2: ATPIX65, next generation Atlas pixel readout prototype To explore the capabilities of advanced CMOS processes to address future HEP needs (upgrades, SLHC, ) To have a feel of what is the best way these processes should be used to maximize ROI. To evaluate radiation hardness (mainly SEU and new damage mechanisms, if any!) To keep abreast of the state of the art (if one can). 22

23. Pixel region (2X2) a la FEI4 if implemented in 65nm  Region logic synthesized from FEI4 verilog.  Neither 100% complete nor verified.  Just to have an idea on what is possible Pixel size=50X100 (?)  ~FEI4 AFE equivalent 23

24. “ FEI5” 2X2 REGION (100X200) Substantial area reduction Ultimately the width of a pixel will be limited by practical considerations (power distribution) and not the number of transistors! Room to add functionality FIE4 pixel region Vs Pix65nm region (assuming y=50u) FEI4 2X2 REGION (100X500) If area to be kept the same as FEI4, about 4X more logic can be added 24

25. Snapshot of submitted pixel array 25  m y cell pitch but 50  m bump y picth. Power distribution will be major factor in the ultimate minimum dimensions Bump mask not part of the submitted layout (same size as FEI4) 25

26. ATPIX65A FEND BLOC DIAGRAM Inject Bloc Preamp. 17fF Feeback cap. Variable “Rff” Single to differential+ Comparator “preamp” Comparator TDAC (+/- 4b tuning) 26 Passive RC: gate leakage limited  Uses only 65nm Transistors  2  A to 25  A @ 1.2V

27. ATPIX65A: Atlas Pixel prototype array Pixels with Added sensors (row 11:31) Pixels with Added mimcaps (31,27,22, 18) 16 X 32 array 25  X 125  pixels 27

28. Preliminary test results Preamp out Single to Diff. out Chan 15/32 Qin: 2ke Chip found to work as expected! VDD=1.2V I= 5  A per pixel (can be as low as 2  A) 28

29. Qin=10ke-; 5IFF settings Chan 15/32 Qin: 2ke to 10ke- 29

30. ATPIX65A: Noise and Threshold distribution Channels with caps or diodes 30

31. ATPIX65A: ENC for some columns.. Channels with mimcaps Channels with Diodes (3 types) 31

32. Fe55 spectrum as detected by one of the integrated sensors 32 Chip2 high gain mode. Sensor@-8V Very preliminary! Work in progress! 1040e- pulser injection ~3.7keV. Assuming Cinj to be nominal. 2154 KeV (2.9KeV? May be partial 5.9KeV charge collection?) 5154 KeV (theory; 5.9KeV?) For the experiment to agree with theory (for the 5.9KeV), injection cap has to be corrected by 15%. Still being reviewed! Noise artificially Limited

33. Example 4: Fast, rad-hard CMOS direct detectors for TE 33 0.35 um CMOS TEAM2k (2009) 9.5  pixels 4Mpix, 400 f/s 0.18 um CMOS K2 sensor (2010) 5  pixels 16Mpix, 400 f/s Improved radiation tolerance Commercial product 0.35 um CMOS(2009) TEAM1k 1 Mpix HIPPIX (2011) 65nm proto Fabrication process Pixel pitch [µm] Conversion Gain [µV/e - ] Noise [e - ] Leakage current [fA] Well depth [e - ] 0.35 µm9.59.4301090000 0.18 µm5.015.535-40423000 65 nm2.52150818000 B.Krieger, TNS 2011

34. Example 4: HIPPO, a column-Parallel CCD readout (for X-ray imaging and Mu2E applications)  Megapixel square sensor has ~1000 columns @ 50 μm pitch  need custom IC readout  No room for output amplifier  need charge-sensitive readout  Ultimate applications require intensive DSP  advanced CMOS process  65nm CMOS found to be the most adequate 35 e - @ 10 Mpix/s Custom 65nm CMOS column-Parallel LBNL CCD 34 C. Grace, TNS 2011

35. HIPPO prototype chip 4 ADCs16 SHAs 16 Analog Front ends 4200 μm SERDES (480 Mb/s) 12b (80 Msps) HV input transistor to achieve the required noise level. Nominal transistor is too leaky! 35

36. HIPPO results (mixed simulation and measurements) Resolution12 b @80MHz Noise0.77 b Linearity10 b Serial output480 Mb/s ADC Pitch200 μm ADC Area0.35 mm 2 Power per ADC30 mW 36 Full Scale50k / 1M e- CCD charge200ke- Input noise35 /24e- Settling time< 15ns Charge loss < 1% Linearity10 b Power5 mW ADC Preamp J.P. Walder, TNS 2011

37. Conclusions 37 Unprecedented advances in IC technology are offering new ways to implement readout systems (for all kind of detector systems). New challenges seem to be more addressable with scaled down technologies. Future systems will require smaller geometries, lower power, higher level of processing, high radiation tolerance, lower cost per function, …etc Among the advantages of newer technologies are: Very high integration density Inherent high radiation tolerance A reasonable number of device types for extra design flexibility Availability of high quality passives A high number of metal levels Skewing the mix of functional blocks towards digital would result in a better area usage and chip yield. Not to mention flexibility (programmability) and Productivity (think advanced digital tools) A myriad of challenges related to ultra complex processes and ultra small devices are associated with these technologies. For some of these, mitigation techniques are readily available A unique challenge to the research community is perhaps the cost of these advanced processes (given the low volume usually involved). Common wisdom applies: for some applications plain old technologies would remain the optimal choice.

38. Acknowledgements 38 Thank You Many Thanks to all people whose work has been mentioned and to my colleagues at LBNL For their help. Please refer to the referenced work for more exciting details.