1. The LC-3 – Chapter 5 COMP 2620 Dr. James Money COMP 2620 1

2. Data Movement Instructions Recall that there are three types of instructions: – Operate instructions – Data movement instructions – Control instructions We consider the data movement instructions today

3. Data Movement Instructions Remember these types of instructions move data from registers to memory and back For now, we will not consider the movement of data from registers to input/output devices We consider only to/from memory to general purpose registers (GPRs)

4. Data Movement Instructions The process of move information from memory to a register is called a load The process of moving information from a register to memory is called a store In both cases, the source operand completely overwrites the destination operand

5. Data Movement Instructions The LC-3 has the following movement instructions: – LD – load PC relative – LDR – load base+offset – LDI – load indirect – LEA – load effective address – ST –store PC relative – STR – store base+offset – STI – store indirect

6. Data Movement Instructions The format of the load and store instructions is Bits [11:9] is first operand, a register – DR = destination register – SR = source register – Depends on whether load or store 1514131211109876543210 OpcodeDR or SRAddress Generation Bits

7. Data Movement Instructions Bits [8:0] contain the address generation bits This encodes the information for the 16 bit address of the second operand There are four ways to interpret this The opcode determines which way these bits are interpreted

8. Base+Offset Mode The LDR (opcode = 0110) and STR (opcode = 0111) use a base + offset addressing mode The name is derived from the fact the final address is given by a base register and a 6 bit signed extended offset from the base

9. Base+Offset Mode The offset portion is a literal or immediate operand using bits [5:0] The base register is specified in bits [8:6] The range of the offset is -32…31 Allows the memory location to be anywhere in address space

10. LDR (Base+Offset)

11. STR (Base+Offset)

12. Base+Offset Mode Assume that R2 has the value 0x2345 Then, the instruction The is LDR R1, R2, 0x1D We use that 0x2345+0x1D = 0x2362 Hence, R1=MEM[0x2362] 1514131211109876543210 01100010100 11101

13. Base+Offset Mode

14. Immediate Mode The last addressing mode is the immediate addressing mode It is used only by load effective address (LEA, opcode = 1110) LEA works by adding the signed extended bits [8:0] to the incremented PC and storing in the register in bits[11:9] There is no memory access!

15. LEA (Immediate)

16. Immediate Mode Consider the instruction: This is LEA R5,-3 So, the result is R5=PC+-3 If the instruction is at 0x4018, R5 will have the value 0x4016 1514131211109876543210 11101011111 11101

17. Immediate Mode

18. Example AddressInstructionComments x30F61 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1  PC – 3 = x30F4 x30F70 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2  R1 + 14 = x3102 x30F80 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[PC - 5]  R2 M[x30F4]  x3102 x30F90 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0 x30FA0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2  R2 + 5 = 5 x30FB0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M[R1+14]  R2 M[x3102]  5 x30FC1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3  M[M[x30F4]] R3  M[x3102] R3  5 opcode