1. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 1 – –Second level Third level – –Fourth level » »Fifth level 1 The Von Neumann Model Proposed in 1946Proposed in 1946 Two main ideas:Two main ideas: components of an architecturecomponents of an architecture how instructions are processedhow instructions are processed

2. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 2 – –Second level Third level – –Fourth level » »Fifth level 2 Basic Architecture memory memory processor processor input input output output control unit control unit contains instructions that comprise a program a program executes the instructions orders the execution of the instructions an instruction is a unit of work

3. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 3 – –Second level Third level – –Fourth level » »Fifth level 3 Organization

4. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 4 – –Second level Third level – –Fourth level » »Fifth level 4 LC-2 Organization

5. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 5 – –Second level Third level – –Fourth level » »Fifth level 5 Memory Recall the 2 2 by 3 memory of Ch. 3Recall the 2 2 by 3 memory of Ch. 3 more realistically, many PCs aremore realistically, many PCs are 2 28 address space (256 MB)2 28 address space (256 MB) 8 bit addressability8 bit addressability LC-2 is 2 16 by 16LC-2 is 2 16 by 16

6. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 6 – –Second level Third level – –Fourth level » »Fifth level 6 Special Registers MAR: memory address registerMAR: memory address register location to be read/writtenlocation to be read/written MDR: memory data registerMDR: memory data register data value to be read/writtendata value to be read/written what has to be asserted for a value to be written?what has to be asserted for a value to be written?

7. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 7 – –Second level Third level – –Fourth level » »Fifth level 7 Contents of Memory/Registers 00 0 1 0 01 1 1 1 10 0 0 1 11 0 0 0 Memory MARMDRWE 0 0 11 1 1 0 0 1 01 1 0 1 Causes memory to be read into MDR Causes memory to be written from MDR 00 0 1 0 01 1 1 1 10 1 1 0 11 0 0 0

8. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 8 – –Second level Third level – –Fourth level » »Fifth level 8 Processing Unit may contain specialized functional units may contain specialized functional units LC-2 ALU has only ADD, AND, NOT operations LC-2 ALU has only ADD, AND, NOT operations size of information processed by ALU size of information processed by ALU is the word length of the computer is the word length of the computer LC-2 has 16 bit word length LC-2 has 16 bit word length

9. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 9 – –Second level Third level – –Fourth level » »Fifth level 9 Registers temporary storage used by CPU for intermediate values of computations temporary storage used by CPU for intermediate values of computations DEC Alpha has 32 registers DEC Alpha has 32 registers LC-2 has 8 (R0-R7) LC-2 has 8 (R0-R7)

10. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 10 – –Second level Third level – –Fourth level » »Fifth level 10 Input/output peripherals that allow computer to be connected to the outside worldperipherals that allow computer to be connected to the outside world get data/programs in and outget data/programs in and out input: keyboard, mouse, scanners, disksinput: keyboard, mouse, scanners, disks output: monitor, printers, disksoutput: monitor, printers, disks floppy, hard drives, zip disks, CDsfloppy, hard drives, zip disks, CDs

11. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 11 – –Second level Third level – –Fourth level » »Fifth level 11 Control Unit keeps track of current instruction in a program and current step in executing an instructionkeeps track of current instruction in a program and current step in executing an instruction coordinates activities between componentscoordinates activities between components registersregisters IR: holds current instructionIR: holds current instruction PC: holds address of next instructionPC: holds address of next instruction

12. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 12 – –Second level Third level – –Fourth level » »Fifth level 12 Discuss LC-2 as an Example of a Von Neumann Architecture some registers not yet discussedsome registers not yet discussed KBSR: status of keys struckKBSR: status of keys struck KBDR: value of key struckKBDR: value of key struck CRTSR: status of monitorCRTSR: status of monitor CRTDR: value to be written on monitorCRTDR: value to be written on monitor

13. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 13 – –Second level Third level – –Fourth level » »Fifth level 13 Central ideas of VN architecture Instructions and data are both sequences of bits stored in memory Instructions and data are both sequences of bits stored in memory One instruction at a time is executed (sequentially) One instruction at a time is executed (sequentially)

14. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 14 – –Second level Third level – –Fourth level » »Fifth level 14 Instruction Processing 2 parts:2 parts: opcode: what is to be doneopcode: what is to be done operands: what data is manipulatedoperands: what data is manipulated LC-2 instruction:LC-2 instruction: [15:12] opcode[15:12] opcode [11:0] how to locate operands[11:0] how to locate operands How many distinct operations in LC-2?How many distinct operations in LC-2?

15. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 15 – –Second level Third level – –Fourth level » »Fifth level 15 ADD Example opcode for ADD is 0001 opcode for ADD is 0001 ADD requires values to be pre-stored in registers, then the result is stored in a register ADD requires values to be pre-stored in registers, then the result is stored in a register Operands from register2 and register 3, result put in register 1 Operands from register2 and register 3, result put in register 1 opcode register 1 register 2 not used register 3 15………12 11……………9 8……….….6 5…..……..3 2………...0

16. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 16 – –Second level Third level – –Fourth level » »Fifth level 16 LDR Example load register with a value from memory load register with a value from memory causes value of 2nd register to be added to offset value, and value at that location is stored in 1st register causes value of 2nd register to be added to offset value, and value at that location is stored in 1st register opcode for LDR is 0110 opcode for LDR is 0110 opcode register 1 register2 offset 15………12 11……………9 8…..…….6 5………….0..

17. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 17 – –Second level Third level – –Fourth level » »Fifth level 17 LDR cont’d 15………12 11……………9 8……………….6 5………………….….0 0110 010 011 000110 0110 010 011 000110 value (2nd register + offset) stored in 1st register contents of memory in location (R3 + 6) goes into R2 called base + offset addressing mode addressing mode: describes the computation needed to yield values for operands

18. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 18 – –Second level Third level – –Fourth level » »Fifth level 18 The Instruction Cycle Sequence of steps carried out by control unit to execute instructions Sequence of steps carried out by control unit to execute instructions called phases called phases 6 phases, all may not be used by each instruction 6 phases, all may not be used by each instruction

19. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 19 – –Second level Third level – –Fourth level » »Fifth level 19 Fetch-Decode-Execute Cycle 1. fetch: gets next instruction from memory into IR MAR PC MDR contents of memory at location given in MAR IR MDR PC PC + 1

20. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 20 – –Second level Third level – –Fourth level » »Fifth level 20 Fetch-Decode-Execute Cycle 2. decode: in LC-2, a 4 to 16 decoder looks at the 4 opcode bits and asserts the appropriate output line to indicate the instruction to be executed 3. evaluate address: if a memory address is to be accessed (as in LDR) this phase computes the address not needed in ADD

21. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 21 – –Second level Third level – –Fourth level » »Fifth level 21 Fetch-Decode-Execute Cycle 4. fetch operands: obtains values of operands 5. execute: carries out instruction in ALU 6. store result: write result to designated destination LDR gets value from memory into a register ADD gets values from registers not needed in LDR increment PC, go to 1

22. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 22 – –Second level Third level – –Fourth level » »Fifth level 22 Changing the Execution Order 2 issues:2 issues: how to alter the execution order?how to alter the execution order? how to stop at the end of a program?how to stop at the end of a program? have to change the PC before the next fetch phasehave to change the PC before the next fetch phase

23. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 23 – –Second level Third level – –Fourth level » »Fifth level 23 Instruction Types 3 kinds of instructions:3 kinds of instructions: operate (e.g., ADD)operate (e.g., ADD) move data (e.g., LDR)move data (e.g., LDR) control instruction (e.g., JMPR)control instruction (e.g., JMPR) control instructions load the PC during the execute phasecontrol instructions load the PC during the execute phase

24. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 24 – –Second level Third level – –Fourth level » »Fifth level 24 JMPR Example puts an address in the PC puts an address in the PC useful for executing loops or skipping around useful for executing loops or skipping around uses base + offset addressing uses base + offset addressing JMPR opcode is 1100 JMPR opcode is 1100 opcode not used register1 offset 15………12 11……………9 8……………….6 5……………….0

25. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 25 – –Second level Third level – –Fourth level » »Fifth level 25 Tying It All Together: Example Algorithm Tying It All Together: Example Algorithm 1. Initialize a counter to 12 and a sum to 0. 2. If counter is 0, go to step 7. 3. else get next data item; 4. add item to sum; 5. decrement counter; 6. Output “sum is:” sum. 7. End

26. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 26 – –Second level Third level – –Fourth level » »Fifth level 26 Machine Language Example 3000 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 3004 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 3006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 3009 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 LEA R1, x3100 AND R3, 0 AND R2, 0 ADD R2, 12 BRz R2, x300A LDR R4, M[R1] ADD R3, R4 ADD R1, 1 ADD R2, -1 BRnzp x3004 Corresponding Assembly Language opcodes

27. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 27 – –Second level Third level – –Fourth level » »Fifth level 27 C++ Example // assumes an array holding 12 integers // has been declared and initialized int sum = 0; for (int i = 0; i < 12; i++) sum = sum + array[i]; LEA R1, x3100 AND R3, 0 AND R2, 0 ADD R2, 12 BRz R2, x300A LDR R4, M[R1] ADD R3, R4 ADD R1, 1 ADD R2, -1 BRnzp x3004

28. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 28 – –Second level Third level – –Fourth level » »Fifth level 28 Example continued 3100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3102 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3103 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3104 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 3105 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 3106 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 3107 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3108 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 3109 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 310A 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 310B 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 310C 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Data memory containing 12 values to sum Register s used R1 – address of data value R2 – number of data values left to add R3 – Sum of values which have been added R4 – current value to add to the sum

29. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 29 – –Second level Third level – –Fourth level » »Fifth level 29 Example continued Contents of Registers, first time thru the loop (in hexadecimal) (in hexadecimal) After instruction 3005 3100 R1 R2 R3 R4 000C 0000 0001 After instruction 3008 3101 R1 R2 R3 R4 000B 0001

30. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 30 – –Second level Third level – –Fourth level » »Fifth level 30 Example continued Contents of Registers, 2 nd time thru the loop (in hexadecimal ) (in hexadecimal ) After instruction 3005 3101 R1 R2 R3 R4 000B 0001 0002 After instruction 3008 3102 R1 R2 R3 R4 000A 0003 0002

31. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 31 – –Second level Third level – –Fourth level » »Fifth level 31 Example continued Contents of Registers, 3 rd time thru the loop (in hexadecimal) (in hexadecimal) After instruction 3005 3102 R1 R2 R3 R4 000A 0003 After instruction 3008 3103 R1 R2 R3 R4 0009 0006 0003

32. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 32 – –Second level Third level – –Fourth level » »Fifth level 32 Example continued Contents of Registers, 12 th time thru the loop (in hexadecimal) (in hexadecimal) After instruction 3005 310C R1 R2 R3 R4 0001 0042 000D After instruction 3008 310D R1 R2 R3 R4 0000 004E 000D

33. Click to edit Master title style Click to edit Master text styles – –Second level Third level – –Fourth level » »Fifth level 33 – –Second level Third level – –Fourth level » »Fifth level 33 Foundation for Programming When you write C++ programs next quarter, you know they are translated to assembly language by a compiler When you write C++ programs next quarter, you know they are translated to assembly language by a compiler then translated to machine language to be executed by the hardware then translated to machine language to be executed by the hardware hardware consists of functional units in Von Neumann architecture hardware consists of functional units in Von Neumann architecture functional units are made up of gates functional units are made up of gates gates are implemented by transistors gates are implemented by transistors