1. ESE534 -- Spring 2014 -- DeHon 1 ESE534: Computer Organization Day 20: April 9, 2014 Interconnect 6: Direct Drive, MoT

2. Previously Tree-based network –O(N) switches with linear population Mesh Interconnect –O(N p+0.5 ) switches with linear population Segmentation in Mesh ESE534 -- Spring 2014 -- DeHon 2

3. Today Directional Drive Mesh-of-Trees (MoT) Multi-level metal Heterogeneous Blocks Unified Network Design (time permit) ESE534 -- Spring 2014 -- DeHon 3

4. 4 Bidirectional Any wire can send data any direction. Horizontal –Can route right or left Vertical –Can route up or down

5. Buffered Bidirectional Wires Logic C Block S Block 5 ESE534 -- Spring 2014 -- DeHon

6. 6 Bidirectional Any wire can send data any direction. Horizontal –Can route right or left Vertical –Can route up or down Pros? Cons?

7. Tristate vs. Buffer Which is faster? ESE534 -- Spring 2014 -- DeHon 7

8. Buffered Switch Composition ESE534 -- Spring 2014 -- DeHon 8 Making a buffer tristateable makes it larger and diminishes its drive strength.

9. Directional Drive Slides and Study from Guy Lemieux (Paper FPT2004 – Tutorial FPT 2009) ESE534 -- Spring 2014 -- DeHon 9

10. Bidirectional Wires Problem Half of tristate buffers left unused Buffers + input muxes dominate interconnect area 10 ESE534 -- Spring 2014 -- DeHon

11. Bidirectional vs Directional 11 ESE534 -- Spring 2014 -- DeHon

12. Bidirectional vs Directional 12 ESE534 -- Spring 2014 -- DeHon

13. Bidirectional vs Directional 13 ESE534 -- Spring 2014 -- DeHon

14. Bidirectional Switch Block 14 ESE534 -- Spring 2014 -- DeHon

15. Directional Switch Block 15 ESE534 -- Spring 2014 -- DeHon

16. Bidirectional vs Directional Switch Element Same quantity and type of circuit elements, twice the wiring Switch Block Directional half as many Switch Elements 16 ESE534 -- Spring 2014 -- DeHon

17. Multi-driver Wiring Logic outputs use tristate buffers (C Block) Directional & multi-driver wiring C Block S Block CLB 17 ESE534 -- Spring 2014 -- DeHon

18. Single-driver Wiring Logic outputs use muxes (S Block) Directional & single-driver wiring New connectivity constraint S Block CLB 18 ESE534 -- Spring 2014 -- DeHon

19. Long Wires in Directional Long wires, span L tiles –Example L = 3 123 CLB 19 ESE534 -- Spring 2014 -- DeHon

20. Directional, Single-driver Benefits Average improvements 0% channel width (most surprising?) 9% delay 14% tile length of physical layout 25% transistor count 32% area-delay product 37% wiring capacitance Any reason to use bidirectional? 20 ESE534 -- Spring 2014 -- DeHon

21. Preclass Complete Table ESE534 -- Spring 2014 -- DeHon 21

22. MoT ESE534 -- Spring 2014 -- DeHon 22

23. ESE534 -- Spring 2014 -- DeHon 23 Recall: Mesh Switches Switches per switchbox: –6w/L seg Switches into network: –(K+1) w Switches per PE: –6w/L seg + Fc  (K+1) w –w = cN p-0.5 –Total  N p-0.5 Total Switches: N*(Sw/PE)  N p+0.5 > N

24. ESE534 -- Spring 2014 -- DeHon 24 Recall: Mesh Switches Switches per PE: –6w/L seg + Fc  (K+1) w –w = cN p-0.5 –Total  N p-0.5 Not change for –Any constant Fc –Any constant L seg

25. ESE534 -- Spring 2014 -- DeHon 25 Mesh of Trees Hierarchical Mesh Build Tree in each column [Leighton/FOCS 1981]

26. ESE534 -- Spring 2014 -- DeHon 26 Mesh of Trees Hierarchical Mesh Build Tree in each column …and each row [Leighton/FOCS 1981]

27. ESE534 -- Spring 2014 -- DeHon 27 MoT Parameterization Support C with additional trees –(like BFT) C=1 C=2

28. ESE534 -- Spring 2014 -- DeHon 28 MoT Parameterization: P P=0.5 P=0.75

29. ESE534 -- Spring 2014 -- DeHon 29 Mesh of Trees Logic Blocks –Only connect at leaves of tree Connect to the C trees –Per side –4C total C<W

30. ESE534 -- Spring 2014 -- DeHon 30 Switches How many switches per tree? How many trees? How many total switches?

31. ESE534 -- Spring 2014 -- DeHon 31 Switches Total Tree switches –2 C  N× (switches/tree) Sw/Tree:

32. ESE534 -- Spring 2014 -- DeHon 32 Switches Only connect to leaves of tree Leaf switches: C  (K+1) Total switches  Leaf + Tree  O(N)  Compare Mesh O(N p+0.5 )

33. ESE534 -- Spring 2014 -- DeHon 33 Wires Design: O(N p ) in top level Total wire width of channels: O(N p ) –Another geometric sum No detail route guarantee (at present)

34. ESE534 -- Spring 2014 -- DeHon 34 Empirical Results Benchmark: Toronto 20 Compare to L seg =1, L seg =4 –CLMA ~ 8K LUTs Mesh(L seg =4): w=14  122 switches/LB MoT(p=0.67,arity=2): C=4  89 switches/LB –Benchmark wide: 10% less CLMA largest Asymptotic advantage [Rubin,DeHon/FPGA2003]

35. MoT Parameters C, P Arity Staggering ESE534 -- Spring 2014 -- DeHon 35

36. ESE534 -- Spring 2014 -- DeHon 36 Staggering With multiple Trees –Offset relative to each other –Avoids worst-case discrete breaks

37. ESE534 -- Spring 2014 -- DeHon 37 Staggering With multiple Trees –(not offset)

38. ESE534 -- Spring 2014 -- DeHon 38 Staggering With multiple Trees –Offset relative to each other –Avoids worst-case discrete breaks

39. ESE534 -- Spring 2014 -- DeHon 39 Staggering With multiple Trees –Offset relative to each other –Avoids worst-case discrete breaks

40. ESE534 -- Spring 2014 -- DeHon 40 Flattening Can use arity other than two

41. ESE534 -- Spring 2014 -- DeHon 41 [Rubin&DeHon/TRVLSI2004] Overall 26% fewer than mesh

42. ESE534 -- Spring 2014 -- DeHon 42 Day 5

43. ESE534 -- Spring 2014 -- DeHon 43 Wire Layers = More Wiring Day 5

44. ESE534 -- Spring 2014 -- DeHon 44 Mesh Segmentation Wires of uniform length L seg Allow wires to bypass switchboxes

45. For Uniform Length Wires How does  Z relate to  X? ESE534 -- Spring 2014 -- DeHon 45 XX ZZ

46. Use of Metal Layers in Mesh Number of metal layers we can use is ultimately limited Uniform wires saturate vias from active layer at bottom ESE534 -- Spring 2014 -- DeHon 46

47. ESE534 -- Spring 2014 -- DeHon 47 MoT Layout Main issue is layout 1D trees in multilayer metal

48. ESE534 -- Spring 2014 -- DeHon 48 Row/Column Layout Geometric Progression  does not saturate via space!

49. ESE534 -- Spring 2014 -- DeHon 49 Row/Column Layout

50. ESE534 -- Spring 2014 -- DeHon 50 Composite Logic Block Tile

51. ESE534 -- Spring 2014 -- DeHon 51 P=0.75 Row/Column Layout

52. ESE534 -- Spring 2014 -- DeHon 52 P=0.75 Row/Column Layout

53. ESE534 -- Spring 2014 -- DeHon 53 MoT Layout Easily laid out in Multiple metal layers –Minimal O(N p-0.5 ) layers Contain constant switching area per LB –Even with p>0.5

54. Compare Mesh Switch area per LB grows O(N p-0.5 ) Ability to use metal layers limited –Saturate vias MoT Switch area per LB constant O(1) Can use growing number of metal layers –While keeping switch area constant ESE534 -- Spring 2014 -- DeHon 54

55. Heterogeneous Blocks ESE534 -- Spring 2014 -- DeHon 55

56. Heterogeneous How integrate heterogeneous blocks? –Memory blocks alongside 4-LUTs –Processors –Custom Units ESE534 -- Spring 2014 -- DeHon 56

57. Replace Clusters Cluster LUTs Replace LUT clusters with other units Requires –same/similar I/O –Network support If replace in row (column) –Change height (width) to adjust for different size ESE534 -- Spring 2014 -- DeHon 57

58. Stratix V Floorplan TODO: commercial example ESE534 -- Spring 2014 -- DeHon 58 Source: http://www.altera.com/devices/fpga/stratix-fpgas/stratix-v/stxv-index.jsp

59. Replace Subtrees ESE534 -- Spring 2014 -- DeHon 59

60. ESE534 -- Spring 2014 -- DeHon Heterogeneous Example Unified Network Fine-grained spatial logic Memory Blocks VLIW temporal processors 60

61. ESE534 -- Spring 2014 -- DeHon 61 Big Ideas [MSB Ideas] Benefits to Single Driver Hierarchy structure –allows to save switches O(N) vs.  (N p+0.5 ) –reduces worst-case switches in path –Can exploit multi-level metal

62. Admin HW8 due today HW9 next Wednesday –Must run tools; will take time (plan for it) Reading for Monday on Web ESE534 -- Spring 2014 -- DeHon 62

63. ESE534 -- Spring 2014 -- DeHon 63 Relation?

64. ESE534 -- Spring 2014 -- DeHon 64 How Related? What lessons translate amongst networks? Once understand design space –Get closer together Ideally –One big network design we can parameterize

65. ESE534 -- Spring 2014 -- DeHon 65 MoT  HSRA (P=0.5)

66. ESE534 -- Spring 2014 -- DeHon 66 MoT  HSRA (p=0.75)

67. ESE534 -- Spring 2014 -- DeHon 67 MoT  BFT A C MoT maps directly onto a 2C HSRA –Same p’s BFT can route anything MoT can

68. ESE534 -- Spring 2014 -- DeHon 68 BFT  MoT Decompose and look at rows Add homogeneous, upper-level corner turns

69. ESE534 -- Spring 2014 -- DeHon 69 BFT  MoT

70. ESE534 -- Spring 2014 -- DeHon 70 BFT  MoT

71. ESE534 -- Spring 2014 -- DeHon 71 BFT  MoT

72. ESE534 -- Spring 2014 -- DeHon 72 BFT  MoT BFT + BFT T = MoT w/ H-UL-CT –Same C, P –H-UL-CT: Homogeneous, Upper-Level, Corner Turns

73. ESE534 -- Spring 2014 -- DeHon 73 HSRA  MoT (p=0.75)

74. ESE534 -- Spring 2014 -- DeHon 74 HSRA  MoT (p=0.75) Can organize HSRA as MoT P>0.5 MoT layout –Tells us how to layout p>0.5 HSRA

75. ESE534 -- Spring 2014 -- DeHon 75

76. ESE534 -- Spring 2014 -- DeHon 76 MoT vs. Mesh MoT has Geometric Segment Lengths Mesh has flat connections MoT must climb tree –Parameterize w/ arity MoT has O(N p-0.5 ) fewer switches

77. ESE534 -- Spring 2014 -- DeHon 77 MoT vs. Mesh Wires –Asymptotically the same (p>0.5) –Cases where Mesh requires constant less –Cases where require same number

78. ESE534 -- Spring 2014 -- DeHon 78 [DeHon/TRVLSI2004]