1. Chapter 6 Analysis of Sequential Systems Sequential Memory Feedback

2. Engineering Takes three approaches 1.Analysis – looks at a system to determine how it works 2.Design – looks at how to make a system 3.Application – looks at integration of existing designs for solution Chapter 6 is analysis Chapter 7 is design Combinational logic uses AND, OR, NOT to create circuit. Sequential logic uses Flip / Flops to create memory. Usually adds combinational as input and output to the memory.

3. Asynchronous - USB Synchronous – Cell phone Frequency = 1/T 200 MHz = 50 microsec “ON” duration can vary Pulse is often choice Power depends on “ON” duration Time Clock Enable Simply another input Leading edge – active high Trailing or falling edge – active low Signal is active as approaches active level Transition not sharp, but has slope

5. CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times. State: what is stored in memory. It is stored in binary devices, but the information to be stored is not always naturally binary. Timing trace: a set of values for the input and output (and sometimes the state or other variables of the system, as well) at consecutive clock times.

6. State table: shows for each input combination and each state, what the output is and what the next state is, that is, what is to be stored in memory after the next clock. State diagram (or state graph): a graphical representation of the state table. Moore machine output occurs at next state Requires one more state (FF) but less logic

7. Mealy machine output occurs at present state + input Requires one less state (FF) but more logic

8. Flip Flops / Latch When S=0, R=1, Q t+1 = 0 When S=1, R=0, Q t+1 = 1 S = Set R = Reset

9. Characteristic Excitation Characteristic Symbol Circuit Table Table Eq. Asynchronous (RS F/F)

10. Characteristic Excitation Characteristic Symbol Circuit Table Table Eq. Synchronous

11. P = (S + Q)´ Q = (R + P)´

12. Q’ = (S + Q)´ Flip flop is a latch triggered by a clock 1. Has feedback 2. Is memory device 3. Holds the state S = set, output q=1 R = reset, output q=0 Q’

13. F/F designs SR is the basic device Q indeterminant w/ SR=11 JK uses feedback to fix D is delay D into S & D’ into R T is toggle T into both J & K Q’

19. q* = S + R´q

23. q* = J´q + K´q

24. D 1 = q 1 q´ 2 + x q´ 1 D 2 = xq 1 z = q´ 2

25. D 1 = q 1 q´ 2 + x q´ 1 D 2 = xq 1 z = q´ 2 PS x=0 1 0 1 q1q1 q2q2 D1D1 D2D2 D1D1 D2D2 q1*q1*q2*q2*q1*q1*q2*q2* z 0001011 0101011 1011110 1100000

26. D 1 = q 1 q´ 2 + x q´ 1 D 2 = xq 1 z = q´ 2 PS x=0 1 0 1 q1q1 q2q2 D1D1 D2D2 D1D1 D2D2 q1*q1*q2*q2*q1*q1*q2*q2* z 00001000101 01001000101 10101110110 11000100010 Moore: Output depends Only on state, So show out inside state

27. Moore machine, output z does not depend on input x J 1 = xK 1 = xB´ J 2 = K 2 = x + A´ z = A + B

28. 1.Row 1,look at both A(1) B(2) 2.Start w/ x=0 3.PS, A=0 B=0 (Qa=0 Qb=0) 4.J1=K1=0 5.J2=K2=1 6.Then from table get NS 7.J1=0, K1=0→ A*=A=0 8.J2=1, K2=1 →B*=B’=1 1.Row 2 2.Start w/ x=0 3.PS, A=0 B=1 (Qa=0 Qb=1) 4.J1=K1=0 5.J2=K2=1 6.Then from table get NS 7.J1=0, K1=0→ A*=A=0 8.J2=1, K2=1 →B*=B’=0 J 1 = xK 1 = xB´ J 2 = K 2 = x + A´ z = A + B PSx=0 1 0 1 ABJ1J1 K1K1 J2J2 K2K2 J1J1 K1K1 J2J2 K2K2 A*B*A*B* z 000011010 010011001 1000001 1100001

29. 1.x=0, look at A (1) only 2.J1=K1=0 3.J2=K2=1 4.Then from table get NS 5.J1=0, K1=0→ A*=A 1.x=1, look at A (1) only 2.J1=1, K1=B’ 3.When B=0, J1=K1 4.A=Toggle 5.When B=1, J1=1, Ka=0 6.A=1 PSx=0 1 0 1 ABJ1J1 K1K1 J2J2 K2K2 J1J1 K1K1 J2J2 K2K2 A*B*A*B* z 0000111111010 0100111011011 1000001111101 1100001011111 J 1 = xK 1 = xB´ J 2 = K 2 = x + A´ z = A + B

30. 1.look at B (2) only 2.When A=0, J2=K2=1 3.B*=toggle 4.When A=1, J2=K2=x 5.for x=0, B*=B 6.for x=1, B*=toggle 7.J1=0, K1=0→ A*=A PSx=0 1 0 1 ABJ1J1 K1K1 J2J2 K2K2 J1J1 K1K1 J2J2 K2K2 A*B*A*B* z 000011111101110 010011101100101 100000111110011 110000101111111 J 1 = xK 1 = xB´ J 2 = K 2 = x + A´ z = A + B

31. PSx=0 1 0 1 ABJ1J1 K1K1 J2J2 K2K2 J1J1 K1K1 J2J2 K2K2 A*B*A*B* z 000011111101110 010011101100101 100000111110011 110000101111111 J 1 = xK 1 = xB´ J 2 = K 2 = x + A´ z = A + B

32. Alternative is use Boolean equations For J-K f/f q*=Jq’ + K’q For this problem A* = JaA’ + Ka’A = xA’ + (xB’)A = xA” + x’A + AB B* = Jb’ + Kb’B = (x + A’)B’ + (x + A’)B = xB’ + A’B’ + x’AB J 1 = xK 1 = xB´ J 2 = K 2 = x + A´ z = A + B PSx=0 1 0 1 ABJ1J1 K1K1 J2J2 K2K2 J1J1 K1K1 J2J2 K2K2 A*B*A*B* z 000011111101110 010011101100101 100000111110011 110000101111111

33. D 1 = xq 1 + xq 2 D 2 = xq´ 1 q´ 2 z = xq 1 Mealy, output z depends on input x, as well as state variables (F/F) So state table will have output for x=0 & for x=1 D f/f, q* = D q 1 * = xq 1 + xq 2 q 2 * = xq´ 1 q´ 2

34. D 1 = xq 1 + xq 2 D 2 = xq´ 1 q´ 2 z = xq 1 State 11 is never reached PS x=0 1 0 1 x=0x=1 q1q1 q2q2 D1D1 D2D2 D1D1 D2D2 q1*q1*q2*q2*q1*q1*q2*q2* z 000001000100 010010001000 100010001001 110010001001 Mealy: Output depends on state & input, So show out on transition

35. D 1 = xq 1 + xq 2 D 2 = xq´ 1 q´ 2 z = xq 1 Glitch z = x q 1 x=1 after q 1 =1 Fixed by next clock PS x=0 1 0 1 x=0x=1 q1q1 q2q2 D1D1 D2D2 D1D1 D2D2 q1*q1*q2*q2*q1*q1*q2*q2* z 000001000100 010010001000 100010001001 110010001001