1. Training LHC Powering - Markus Zerlauth Powering Interlocks Markus Zerlauth AB/CO/MI

2. Training LHC Powering - Markus Zerlauth2 Power converters, magnet protection and powering interlocks UA83 Quench Detector Quench Heater PS Quench Detector Quench Heater PS Power Converter Tunnel Cryo OK UPS / AUG OK QPS OK Permit Powering Energy Extraction QPS Controller Quench Detector Arc cryostat DFBAO Powering Interlocks Karl-Hubert Amalia/Luigi David Rudiger Thomas Reiner

3. Training LHC Powering - Markus Zerlauth3 Outline Why do we use Powering Interlock Systems for the LHC? Main functionalities of the system in the LHC powering Hardware Architecture and Hardwired interlock loops What is an interlock type A, B1, B2 and C? Links with other systems, AUG / UPS, cryogenics Constraints on operation and commissioning and Startup interlocks Supervision application

4. Training LHC Powering - Markus Zerlauth4 Main functionalities & requirements Powering Interlock Controllers (PIC) assure that all conditions for safe magnet powering are met –Upon Start-up –During operation Protection on a circuit by circuit basis Additional protection mechanisms on a powering subsector basis Linking magnet powering to technical services & safety systems (UPS, AUG, Cryogenics) Linking magnet powering to beam interlock system Provide the evidence of powering failures to the operator

5. Training LHC Powering - Markus Zerlauth5 Conditions for powering Cryogenics: Magnet and current leads must be at correct temperature Power converter: must be ready (including cooling water etc.) Quench protection system: must be ready (quench heaters charged, extraction switch closed) Quench in a magnet inside the electrical circuit Warming up of the magnet due to failure in the cryogenic system Warming up of the magnet due to quench in an adjacent magnet AUG or UPS fault Power converter failure Powering Interlock Controller (PIC) Safety systems: must be ready (AUG – arret urgence general, UPS – uninterruptible power supplies, …) Power converters Energy extraction Operator / Controls: must give permission to power

6. Training LHC Powering - Markus Zerlauth6 QPS PC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT DISCHARGE_REQUEST PC_DISCHARGE_REQUEST Powering Interlocks – the circuit level PIC Magnet Cryostat Magnet DFB Magnet … All conditions met for powering: PC_PERMIT Sum of internal converter faults: POWERING_FAILURE Magnet quench or Fast Abort from PIC: PC_FAST_ABORT Loss of coolant: PC_DISCHARGE_REQUEST No direct connection Magnet Protection – Converters (as e.g. in SPS), but use of industrial controllers (PLCs) Protection signals are exchanged via hardwired current loops Depending on stored energy, circuit complexity, QPS, etc.. in between 2-4 signals are exchanged / circuit Naming DB Naming DB for official signal names

7. Training LHC Powering - Markus Zerlauth7 PC QPSPICPC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT DISCHARGE_REQUEST PC_DISCHARGE_REQUEST Interlock Type A (=13kA main + IT) QPSPICPC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT Interlock Type B1 (=600A EE, 600A no EE, 600A no EE crowbar + all dipoles of IPQD) QPSPICPC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT_B2 PC_FAST_ABORT Interlock Type B2 (=all quads of IPQD) PICPC POWERING_FAILURE PC_PERMIT Interlock Type C (= 80-120A) Interlock Types PC_PERMIT_B1

8. Training LHC Powering - Markus Zerlauth8 Hardwired signals - Power Permit Loop Powering Interlock Controller GND +15,,, 24 V Power Converter ST_UNLATCHED:PWR_PERMIT Signal present: Powering permitted Signal to FALSE: Powering not permitted (latched) Powering Permit: CMD_PWR_PERM_PIC Switch closed: permission for powering Switch open: no permission for powering LHC-D-ES-0003-10-02 by R.Schmidt Cable PIC-PC

9. Training LHC Powering - Markus Zerlauth9 Hardwired signals – Circuit Quench Loop Circuit Quench ST_CIRCUIT_OK_QPS Switch closed: no quench Switch open: quench Powering Interlock Controller GND +15,,, 24 V Power Converter ST_FAULTS:FAST_ABORT Signal present: no Fast Power Abort Signal to FALSE: Fast Power Abort (latched) Signal present: no Fast Power Abort ST_ABORT_PIC Signal not present: Fast Power Abort PIC Fast Power Abort Request CMD_ABORT_PIC Switch closed: operation ok Switch open: Fast Power Abort Quench detection Energy extraction 600 A ST_FAST_POWER_ABORT Signal present: no Fast Power Abort Signal to FALSE: Fast Power Abort

10. Training LHC Powering - Markus Zerlauth10 Physical installations in RR77 600A EE system 600A converter QPS 600A protection unit Powering Interlock System

11. Training LHC Powering - Markus Zerlauth11 Physical installations in RR77 Patch Panels Industrial Controller

12. Training LHC Powering - Markus Zerlauth12 Cryostats and interlock systems in sector 7-8 ML8 A78 XL8 Point 7 (Ferney) Point 8 (Leclerc) 3 powering subsectors - XL8(DFBXG) - ML8(DFBMA,DFBMC) - A78(DFBAO-DFBAN- DFBMH) view from outside LHC ring CIP.XL8 CIP.ML8 CIP.AL8 CIP.AR7

13. Training LHC Powering - Markus Zerlauth13 Architecture 28 powering subsectors 36 interlock controllers (2 for long arcs) 5-43 circuits / controller

14. Training LHC Powering - Markus Zerlauth14 PC QPS 1 PIC PC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT DISCHARGE_REQUEST PC_DISCHARGE_REQUEST Powering Interlocks – ‘global’ interlocks Magnet Cryostat Magnet DFB Magnet … CRYO_MAINTAIN PLC-PLC connection in between interlocks and cryogenics 1 signal / powering subsector Creates a slow power abort in ALL circuits of the subsector Global interlocks In addition to circuit/circuit treatment, global interlocks will provoke runtime aborts of ALL circuits in a subsector Exchanged via hardware or between PLC-PLC x N x M

15. Training LHC Powering - Markus Zerlauth15 Powering Interlocks – ‘global’ interlocks UPS_OK Hardwired interlock, connecting all redundant UPS systems of an LHC point + related alcoves 1 signal / LHC point, seen by all powering subsectors Creates a fast power abort in ALL circuits of the subsectors AUG_OK Hardwired interlock, connecting all AUG chains of an LHC point 1 signal / LHC point, seen by all powering subsectors Creates a fast power abort in ALL circuits of the subsectors Quench Propagation From String 2 experience -> Anticipate circuit aborts to avoid additional quenches in adjacent magnets 1 signal / powering subsector Creates a fast power abort in ALL circuits of the subsectors

16. Training LHC Powering - Markus Zerlauth16 QPS PIC PC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT DISCHARGE_REQUEST PC_DISCHARGE_REQUEST Powering Interlocks – start-up interlocks Tunnel – Hardwired signal exchange Surface – ‘Software’ signal exchange QPS SCADA PIC SCADA QPS_OK Start-up interlock, exchanged in between PVSS applications 1 signal / circuit, assuring full redundancy and operation of related QPS equipment If lost during powering, no abort Start-up interlocks In addition to hardwired interlocks, several software interlocks exist Exchanged via CMW, DIP, etc between SCADA systems Verified ONLY upon start-up, thus not provoking aborts during powering

17. Training LHC Powering - Markus Zerlauth17 QPS PIC PC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT DISCHARGE_REQUEST PC_DISCHARGE_REQUEST Powering Interlocks – start-up interlocks Tunnel – Hardwired signal exchange Surface – ‘Software’ signal exchange QPS SCADA PIC SCADA CRYO_START Start-up interlock, exchanged in between PVSS applications 1 signal / subsector, assuring cryogenic conditions of subsector before start-up If lost during powering, no abort CRYO SCADA CRYO_START

18. Training LHC Powering - Markus Zerlauth18 Powering Interlocks – start-up interlocks UPS_START Start-up interlock, exchanged in between SCADA applications 1 signal / subsector, assuring full redundancy of UPS systems CABLE_CONNECT Start-up interlock, verification that all required cables are connected to interlock system 1 signal / cable CONFIG_DATA Start-up interlock, verification that all configuration data of an interlock system is consistent 1 flag / system

19. Training LHC Powering - Markus Zerlauth19 Constraints on circuit powering – Use Case Type A Type B2 Type B1 Type C

20. Training LHC Powering - Markus Zerlauth20 Constraints on circuit powering – Use Case Type B1 Typical Sequence 1.Verify no Global interlock is pending 2.Close EE systems (if existing) and re-arm QPS system via QPS supervision 3.Unlatch Interlocks (SIGNAL Init) 4.Clear PC faults (equipment stop, OFF to converter) 5.-> Circuit ready for powering 1. 3.

21. Training LHC Powering - Markus Zerlauth21 Constraints on circuit powering – Use Case Typical Sequence 6.Verify no Start-up interlock is pending 7.If circuit ‘ready to permit’ 8.Give Permit 6. 7. 8.

22. Training LHC Powering - Markus Zerlauth22 PVSS Expert screens & History Buffer

23. Training LHC Powering - Markus Zerlauth23 Conclusions Powering Interlock system along with its clients assures all conditions for safe powering are met at any time Safety critical protection on a circuit / circuit level via hardwired interlocks Additional software interlocks for start-up –During commissioning ONLY, some of these start-up interlocks can be masked by the expert After interlock commissioning (PIC1 and PIC2, see later presentations), system is considered operational No modifications or tampering with interlocks after this phase

24. Training LHC Powering - Markus Zerlauth24 Questions?

25. Training LHC Powering - Markus Zerlauth25 Glossary Powering Interlocks Powering Interlock Controller Programmable Logic Controller (PLC) Powering Subsector PVSS supervision Interlock Types Hardwired interlocks Global Protection mechanism Quench Propagation Current Loops AUG, UPS, Cryogenics, QPS Startup Interlocks Runtime Interlocks

26. Training LHC Powering - Markus Zerlauth26 Documentation Specification for HW Interfaces of the PIC: EDMS DocNr.:LHC-D-ES-0003 Hardware Interfaces with UPS/AUG: EDMS DocNr.:LHC-CIP-ES-0001 General procedure for HW commissioning: EDMS DocNr.:LHC-D-HCP-0001 Specification for Interlock commissioning procedures: EDMS DocNr.:LHC-D-HCP-0002 Procedures for automated commissioning: EDMS DocNr.:LHC-D-HCP-0005 Powering Subsectors in the LHC: EDMS DocNr.:LHC-D-ES-0002 PIC configuration files: http://cs-ccr-oas2/PIC/listpicnames.dohttp://cs-ccr-oas2/PIC/listpicnames.do PIC layout configuration + Electrical Circuits: http://layout.web.cern.ch/layout/ http://layout.web.cern.ch/layout/