1. Defect-tolerant FPGA Switch Block and Connection Block with Fine-grain Redundancy for Yield Enhancement Anthony J. YuGuy G.F. Lemieux August 25, 2005

2. FPL'05 - Presentation 2 Outline Introduction and Motivation Previous Approaches Fine-grain Redundancy ResultsConclusions

3. FPL'05 - Presentation 3 Introduction and Motivation Scaling introduces new types of defects Smaller feature sizes susceptible to smaller defects Expected results –Defects per chip increases –Chip yield declines FPGAs are mostly interconnect FPGAs must tolerate multiple interconnect defects to improve yield (and $$$)

4. FPL'05 - Presentation 4 General Defect Tolerant Techniques Defect-tolerant techniques minimize impact (cost) of manufacturing defects FPGA defect-tolerance can be loosely categorized into three classes: –Software Redundancy – use CAD tools to map around the defects –Hardware Redundancy – incorporate spare resources to assist in defect correction (eg. Spare row/column) –Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)

5. FPL'05 - Presentation 5 Previous work – 1 – Xilinx Xilinx’s Defect-Tolerant Approach –Customer (knowingly) purchases “less that perfect” parts Customer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstream –Sells FPGA parts that “appear” perfect –Defects avoid the bitstream Limitation: –Chips work only with given bitstream – no changes!

6. FPL'05 - Presentation 6 Previous work – 2 – Altera Altera’s Defect-Tolerant Approach –Customer purchases “seemingly perfect” parts Make defective resources inaccessible to user Coarse-grain architecture –Spare row and column in array (like memories) Defective row/column must be bypassed –Use the spare row/column instead Limitation: –Does not scale well (multiple defects)

7. FPL'05 - Presentation 7 Objective Problem –FPGA yield is on decline because of aggressive technology scaling Proposed Solution –Defect-tolerance through redundancy Important Objectives –Interconnect defects important (dominates area) –Tolerate multiple defects (future trend) –Preserve timing (no timing re-verification) –Fast correction time (production use)

8. FPL'05 - Presentation 8 Our Proposed Solution Fine-grain Redundancy (FGR) – Defect Avoidance by Shifting

9. FPL'05 - Presentation 9 Island-style FPGA

10. FPL'05 - Presentation 10 Directional Switch Block

11. FPL'05 - Presentation 11 Directional Switch Block

12. FPL'05 - Presentation 12 Defect-tolerant Switch Block

13. FPL'05 - Presentation 13 HSPICE Schematic

14. FPL'05 - Presentation 14 Switch Implementation Options Several detailed implementations are possible Trade off area / delay / yield(repairability)

15. FPL'05 - Presentation 15 Defect Avoidance – Switch Implementation Option 1 Can avoid contention by pre-shifting the red signal… OR… [ lower area overhead, lower yield improvement ]

16. FPL'05 - Presentation 16 Defect Avoidance – Switch Implementation Option 2 …OR … can avoid contention by embedding the IMUX [ higher area overhead, best yield ]

17. FPL'05 - Presentation 17 Results AreaDelay Area Delay Product YieldSummary

18. FPL'05 - Presentation 18 Area Results

19. FPL'05 - Presentation 19 Delay Results

20. FPL'05 - Presentation 20 Area-Delay Product

21. FPL'05 - Presentation 21 Yield – 1 Switch Implementation Affects Yield * Assumes all bridging defects

22. FPL'05 - Presentation 22 Yield – 2 Larger Arrays Tolerate More Defects

23. FPL'05 - Presentation 23 Summary

24. FPL'05 - Presentation 24 Conclusions FGR meets desired objectives –Tolerates multiple randomly distributed defects –Defect correction does not perturb timing –Tolerates an increasing number of defects as array size increases –Correction can be applied quickly FGR has different implementation options –Trade-offs between yield, area and delay can be made –Best Area: EN11 –Best Delay: EM11 –Best Yield: EM22

25. Thank you! anthonyy@ece.ubc.ca

26. FPL'05 - Presentation 26 Single-length Defects

27. FPL'05 - Presentation 27 Double-length Defects

28. FPL'05 - Presentation 28 Minimum Fault-free Radius (MFFR)