1. Design + System Drivers Update Design ITWG ITRS Public Conference Hsinchu, 5 Dec 2012
Good morning. Here we present the work that the ITRS Design TWG has pursued in 2007, and describe the continuation of this work into our 2008 strategy.

2. Past Trajectory (2004-2011) 1. Increasingly quantitative roadmap 2
Past Trajectory ( ) Increasingly quantitative roadmap 2. Increasingly complete driver set 3. Increasing MTM content
2011
MTM
roadmap
RF+AMS Driver continued
Updated
Drivers
(MPU, SoC,…)
Upgraded DFM, SL, verification sections
Power design technology roadmap
2010
2009
MTM
RF+AMS Driver start
Updated
Consumer SOC and
MPU Drivers
Upgraded
RF+AMS section
2008
MTM extension
+ iNEMI synch
+ SW !!
MTM
extension
+ iNEMI
+ SW !!
2007
More Than
Moore
(MTM)
analysis
+ iNEMI
Updated
Consumer
Stationary,
Portable architecture,
and
Networking
Drivers
2006
Consumer
Stationary,
Portable,
Networking
Drivers
Updated
Consumer
Stationary,
Portable,
and
Networking
Drivers
2005
Consumer
Stationary,
Portable,
Networking
Drivers
This is a description of Design TWG work over the years (focus on system drivers piece of it). As this slides summarizes, we have been following a consistent successful strategy in the last years. First, we have been assembling a quantified Design Technology roadmap, one that resembles in structure the other non-Design chapters in our roadmap. Second, we have been assembling a comprehensive set of system drivers aligned by segment, thereby mirroring the increasing segmentation in the semiconductor industry.
In 2010 we started working on additional More Than Moore content, including RF+AMS integration, updated some of our key system drivers and design productivity roadmap, and started looking into a “power roadmap” that lines up with our design cost roadmap, which will be published this year !
Consumer
Stationary,
Portable
Drivers
2004
Consumer
Portable
Driver
Additional
Design
Metrics
DFM
Extension
System level extension
System
Drivers
Chapter
Driver
study
Revised
Design
Technology
Metrics
Revised
Design
Metrics
DFM
extension
Revised
Design
metrics
Explore
Design
metrics
Design
Technology
metrics
Design
Chapter 2 2 2

3. Work Toward 2013 and Beyond Design Chapter System Drivers Chapter
Version 2 of the Power-Aware Design Technology roadmap
Version 2 of the 3D IC design technology roadmap
Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS)
Updates of LCP, DFT, Design Verification, Design for Resilience
Design of on-chip memory hits the wall at 16nm HP
System Drivers Chapter
Rethinking the MPU Driver: Core + LLC + “uncore”; microserver class
Revising the SOC-Consumer Portable Driver
Elimination of SOC-Networking, SOC-Consumer Stationary drivers ?
Update of Embedded Memory
Continue development of AMS/RF “sub-driver” of SOC-CP Driver
Cross-TWG
CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices
How will FinFET, UTBB SOI timing change PPA projections?
Renewal of the PIDS HP, LP roadmaps (compact modeling interaction)
3D effort with other TWGs
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 3

4. Work Toward 2013 and Beyond Design Chapter System Drivers Chapter
Version 2 of the Power-Aware Design Technology roadmap
Version 2 of the 3D IC design technology roadmap
Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS)
Updates of LCP, DFT, Design Verification, Design for Resilience
Design of on-chip memory hits the wall at 16nm HP
System Drivers Chapter
Rethinking the MPU Driver: Core + LLC + “uncore”; microserver class
Revising the SOC-Consumer Portable Driver
Elimination of SOC-Networking, SOC-Consumer Stationary drivers ?
Update of Embedded Memory
Continue development of AMS/RF “sub-driver” of SOC-CP Driver
Cross-TWG
CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices
How will FinFET, UTBB SOI timing change PPA projections?
Renewal of the PIDS HP, LP roadmaps (compact modeling interaction)
3D effort with other TWGs
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 4

5. Design Cost Roadmap
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 5

6. Design Power Roadmap
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 6

7. Low-Power Design Technology Roadmap
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables.
NEW: approximate computing, adaptivity, power gating
replacement, dark silicon, extreme heterogeneity, … 7

8. NEW in Low-Power Design Tech Roadmap
Approximate Computing
Variable-accuracy computing (e.g., flexibly from 64b 16b)
4D computing: reconfiguration on the fly
AVS ? (e.g., part of DVFS) Margin reduction?
Adaptivity
Recapture overdesign from wearout, variation margins
Power Gating Replacement
HVT device as power switch hits headroom, area wall  ?
Dark Silicon
“normally-off computing” = “extreme power gating”
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 8

9. “Dark Silicon” Analysis in 2001 ITRS
Power management gap  amount of (switched) logic content in an SOC goes to zero
Challenge: keeping the chip value above zero
Today: turn on only 2-6% of logic on SOC !

10. NEW in Low-Power Design Tech Roadmap
Approximate Computing
Variable-accuracy computing (e.g., flexibly from 64b 16b)
4D computing: reconfiguration on the fly
AVS ? (e.g., part of DVFS) Margin reduction?
Adaptivity
Recapture overdesign from wearout, variation margins
Power Gating Replacement
HVT device as power switch hits headroom, area wall  ?
Dark Silicon
“normally-off computing” = “extreme power gating”
Extreme Heterogeneity
“coprocessor-dominated architectures”
(pervasive heterogeneity; energy-efficiency from specialization; HW accelerators)
“10 x 10”, “13 dwarves”, …
Intel “accelerators for MPU” vs. Tensilica (or, GPUs, xPUs)
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 10

11. Design Tech for More Than Moore Fabrics
Key areas: SW, AMS/RF, MEMS, 3D / novel packaging
Current design technology still insufficient; must broaden beyond current ideas
New 3D / TSV design flows
New multi-physics modeling, simulation, analysis tools
Example: thermal / mechanical analysis (base station)
Example: MEMS + electrical analysis (mobile gaming)
Example: sensors + signal processing (industrial, medical)
Example: software + HW simulation (data center network)
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 11

12. Memory as a Key Factor in Future DT
Physical
Device
Gate
Chip
Bit Cell
Circuit
Array
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables.
Figure DESN12 Possible Variability Abstraction Levels 12

13. Memory as a Key Factor in Future DT
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables.
Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types 13

14. Memory Design Hits The Wall
SRAM hits a brick wall at ~16nm M1 HP
Area overhead: discrete fin sizing to meet stability targets
Vccmin(SRAM)  > Vddmin(logic) due to variability  need assist structures, 8T, or 10T structures for 20nm and beyond
Increased leakage due to increased Vccmin(SRAM) and Vt tradeoffs
eDRAM, L3 (SRAM), L2 (SRAM) subsystem replacements
STT-RAM – density, non-volatility (~low leakage)
FLASH  RRAM
Exploiting 3D integration (monolithic, TSV) schemes
Logic, register files, L1
Power gating strategies
Backup strategies for retention (transfering data to STT-RAM before power-off)
Implications for memory hierarchy, architecture, design
Different sizing of memory subsystems to reflect the energy/latency tradeoffs
Multi-physics models to analyze Vccmin(SRAM)
Exploiting nonvolatility and fine-grain power gating in logic circuits
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 14

15. Work Toward 2013 and Beyond Design Chapter System Drivers Chapter
Version 2 of the Power-Aware Design Technology roadmap
Version 2 of the 3D IC design technology roadmap
Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS)
Updates of LCP, DFT, Design Verification, Design for Resilience
Design of on-chip memory hits the wall at 16nm HP
System Drivers Chapter
Rethinking the MPU Driver: Core + LLC + “uncore”; microserver class
Revising the SOC-Consumer Portable Driver
Elimination of SOC-Networking, SOC-Consumer Stationary drivers ?
Update of Embedded Memory
Continue development of AMS/RF “sub-driver” of SOC-CP Driver
Cross-TWG
CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices
How will FinFET, UTBB SOI timing change PPA projections?
Renewal of the PIDS HP, LP roadmaps (compact modeling interaction)
3D effort with other TWGs
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 15

16. Changes to MPU Model Item Current 2011 model Proposed 2013 model
Die area
140mm2 (CP), 260mm2 (HP)
Area ratio
Core :: 1
Core : LLC : UnCore :: 1: 1: 1
LLC NA
12MB (2011) + 1.4x every tech node
[Borkar10, Borkar07]
UnCore
Uncore Scaling
SRAM A-factor (USRAM)
60F2 (6T), 84F2 (8T) (bulk)
60F2 (6T), 84F2 (8T) (bulk, FinFET)
40F2 (6T), 56F2 (8T) (high-density FinFET) ***
* CP – Cost-Performance; HP – High Performance
** L2$ and L1$ is per core

17. Updated MPU Model: UnCore Scaling
“Uncore” (increasing portion of MPU) consists of:
Memory controller(s)
Graphics and display controller(s)
I/O and bus interface controller(s)
Item
Proposed model
Memory controller
N/2 (CP), N (HP); N = # cores
[Borkar07, Borkar11, 80-core, IVB]
Graphics and Display controller
2x every tech node
[NHM, SNB, NVIDIA]
I/O and bus interface controller
N/6
[SNB, IVB]
Logic (# transistors) growth
Same as core
Logic density
SRAM (# bitcells) growth
512MB * # GPU-Cores
[IVB, NVIDIA]
SRAM density

18. New Drivers Catching Up to “Old” Ones ?
“SoC-ification” of Drivers brings similarities
Need to isolate the parameters driven by each (and only) driver
There are 2 dimensions in the ITRS driver space
There are fabrics, components to built systems on chip (or on package)
There are market domains, which results in architectural templates or “canonical SoCs”.
The creation of new drivers is determined by whether a specific market will be driving a fundamental parameter in our roadmap.
The consumer driver is relatively mature at this point and has been a main focus of attempting to coordinate with iNEMI’s consumer/portable emulator. 18

19. New Drivers Replacing “Old” Ones ?
Potential future system driver list (Markets dimension)
High performance computing MPU – “Office/Server”
Mobile (Application) MPU – “Consumer Portable”
Low power computing MPU – “Microserver”
There are 2 dimensions in the ITRS driver space
There are fabrics, components to built systems on chip (or on package)
There are market domains, which results in architectural templates or “canonical SoCs”.
The creation of new drivers is determined by whether a specific market will be driving a fundamental parameter in our roadmap.
The consumer driver is relatively mature at this point and has been a main focus of attempting to coordinate with iNEMI’s consumer/portable emulator. 19

20. SoC  MPU Convergence: MicroServers ?
Observation: “mobile” computing SoCs competing in server space
Beginning to be used in data centers and cloud computing
Extreme core efficiency (active power < 4W, sleep power < 0.5W)
#Cores, frequency scaling similar to conventional MPUs
Microserver product class (Calxeda, Marvell, Intel, …)  re-examine the MPU model – or possibly create a new driver !
Clock frequency growing at 1.5X every 2 years
Number of cores growing at 2X every 4 years
Networking-like SoC scaling: off-chip latency, accelerators, L3 cache
Power budget under 4W per core (HPC example)
Off-chip bandwidth as high as 200+ Gbps
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 20

21. System Drivers – So Many ?
Fabs will be filled primarily by 2-3 major applications
Fabrics
MPU
PE/DSP
Memory
There are 2 dimensions in the ITRS driver space
There are fabrics, components to built systems on chip (or on package)
There are market domains, which results in architectural templates or “canonical SoCs”.
The creation of new drivers is determined by whether a specific market will be driving a fundamental parameter in our roadmap.
The consumer driver is relatively mature at this point and has been a main focus of attempting to coordinate with iNEMI’s consumer/portable emulator.
AMS
Markets
Medical
Automotive
Network
Office/
Server
Consumer/
Mobile
Consumer
Stationary
A&D 21

22. System Drivers – So Many ?
Fabs will be filled primarily by 2-3 major applications
Drivers will follow suit – applications drive technology
Fabrics
MPU
PE/DSP
Memory
There are 2 dimensions in the ITRS driver space
There are fabrics, components to built systems on chip (or on package)
There are market domains, which results in architectural templates or “canonical SoCs”.
The creation of new drivers is determined by whether a specific market will be driving a fundamental parameter in our roadmap.
The consumer driver is relatively mature at this point and has been a main focus of attempting to coordinate with iNEMI’s consumer/portable emulator.
AMS
Markets
Medical
Automotive
Network
Office/
Server
Consumer/
Mobile
Consumer
Stationary
A&D 22

23. Evolution of System Drivers Inventory
Upcoming years may see a smaller list of key Drivers
As fabs consolidate, applications and drivers do so as well
All remaining applications will ride on existing technology curve
System Driver (Market based)
Technology Parameters Driven
Potential action
High performance (computing) MPU
Frequency, number of cores, memory architecture
Keep
Mobile / consumer MPU
Leakage power efficiency
Low power computing MPU “Microserver”
Operating power efficiency
Introduce?
Networking switch
Number of I/Os / total I/O BW
Keep?
Various fabrics (memory, AMS)
Various fabric-specific parameters
Networking MPU
Number of cores, I/O BW
Keep??
There are 2 dimensions in the ITRS driver space
There are fabrics, components to built systems on chip (or on package)
There are market domains, which results in architectural templates or “canonical SoCs”.
The creation of new drivers is determined by whether a specific market will be driving a fundamental parameter in our roadmap.
The consumer driver is relatively mature at this point and has been a main focus of attempting to coordinate with iNEMI’s consumer/portable emulator. 23

24. SOC-CP Model Revision SoC-CP model Qualitative changes in SoC-CP
High resolution, large screen size video interface require high performance GPU
Cloud-based service over wireless connection eliminates dedicated PEs for speech, character and image recognition, dictionary, etc.
SoC-CP model
Current model: CPU + PE + Peripheral (+ RF, AMS)
Next model: CPU + GPU + Logic Block IO Peripheral
+ Baseband
(+ RF, AMS)
2D/3D graphics
Audio codec, Video codec, Security
DRAM-IF, USB, MIPI, HDMI, LVDS…
Multi-band multi-protocol SDR

25. More Than Moore – AMS/RF “Subdriver”
Several emphases in DT, DFT: System verification, Hetero systems
Plan: paste high-level block model from AMS/RF -- “core model”
Hope to obtain model from additional groups, market analysis
E.G. WiFi/GPS/cellular/BT/NFC front-end blocks, tuner/demodulator blocks 25

26. Work Toward 2013 and Beyond Design Chapter System Drivers Chapter
Version 2 of the Power-Aware Design Technology roadmap
Version 2 of the 3D IC design technology roadmap
Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS)
Updates of LCP, DFT, Design Verification, Design for Resilience
Design of on-chip memory hits the wall at 16nm HP
System Drivers Chapter
Rethinking the MPU Driver: Core + LLC + “uncore”; microserver class
Revising the SOC-Consumer Portable Driver
Elimination of SOC-Networking, SOC-Consumer Stationary drivers ?
Update of Embedded Memory
Continue development of AMS/RF “sub-driver” of SOC-CP Driver
Cross-TWG
CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices
How will FinFET, UTBB SOI timing change PPA projections?
Renewal of the PIDS HP, LP roadmaps (compact modeling interaction)
3D effort with other TWGs
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 26

27. A-Factor Updates (e.g., FinFET)
Ongoing for 2013 revision
Initial draft models developed in April 2012
Many issues to work through
Gridded layout with device grid, metal grid alignment
Dummy poly isolation
Unimportant design rules become important – e.g., gate contact to active contact spacing
SRAM devices have integral sizing, no Vt control except with Lgate biasing
 challenge to maintaining SRAM A-Factor
Current densities and resistivity
 CD (width) scaling of VDD, VSS traces
Comprehension of wiring loads in future designs
Specs for high-performance, low-power cell libraries

28. Device Model / PIDS interaction
Agreed to only one low power device in the roadmap
Removed LOP device flavor  from 3 to 2 devices
Still questioning how much CD variation can be tolerated
Should Design content change as we move toward 450 mm ?
Should Design care about node definitions ?
(foundry names vs. ITRS)
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 28

29. Beyond 2020 Observation: 14 years to get beyond-CMOS idea to products
ITRS groups must start to think about and act on beyond-2020 devices and their use in design
(“technology” by itself is not a complete solution)
What will be the earliest insertions into which products?
MRAM replaces SRAM
3D with vertical nanowires (7nm) bring BEOL interfacing challenge (and: P, N in different vs. same layers?)
Spintronics
Demands Design ITWG collaboration with PIDS, Litho, Interconnect, ERD/ERM – and expanding the scope of ITRS

30. Summary: 2012 Design / SysDrivers Messages
Design technology continues on roadmap of low-power techniques
Design ITWG still clarifying impact of new devices (FinFET A-factor)
Design technology for 3D continues to spread across chapter
Design technology for resilience a fundamental portion of DFM
More Than Moore fabrics will require increasingly specialized DT
Memory an increasingly important factor for design technology
Still pushing to integrate AMS/RF on SoC/SiP despite 3D prospects
System Drivers: SoC-CP revision – and will soaring applications (DTV, microservers) overhaul the driver list ?
ITRS groups must think about Beyond-CMOS based products and insertion points
While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables. 30

31. THANK YOU

32. System – Device Domain Space
Systems
Market
requirements
ICs
System
Demand
Will drive
device
demand
Tech
requirements
Conclusion – what would we like from iNEMI here ? A MAPPING between our template / driver and your emulator (consumer, we think). At the least power consumption ! What is the system saying about max power consumption for this critical chip in a mobile consumer product ? Some work was done but limited – we would like to see specific parameters in your emulators directly constraining the chip we are modeling. 2W ? 1 W ? Of what kind of power ? (standby, maximum, etc.)
Chip level
System level 32